Transcript No Slide Title

Optical I/O Technology for
Chip-to-Chip Digital VLSI
Ian Young
Intel Fellow
Director, Advanced Circuits and Technology Integration
Logic Technology Development
Feb 23rd 2004
What are We Announcing?
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Intel has made significant progress demonstrating the
feasibility of optical chip-to-chip interconnect at data
rates over 1 Giga-Transfers per second.
Optical chip-to-chip interconnect may offer a faster,
cheaper, better alternative to metal-based data buses
between CPU and it’s supporting chips
The demonstration was done with 0.18mm-CMOS
transceiver, with on-chip laser drivers, input amps, and
self-test features. The transceiver chip is integrated with
the optical emitters, detectors, and wave-guides in a
hybrid package
This optical I/O implementation is highly compatible with
CPU architecture, process, and packaging
This announcement is a progress report from Intel’s
Component’s Research Lab. Intel has not made a
determination on product plans based upon these
results.
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Why is this Important?
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Individual bus speed between microprocessor and
chipset will increase an order of magnitude in the next
7-10 years.
With such high speeds, Copper interconnects on a
mother board will be bandwidth-limited due to:
– Signal attenuation and distortion (signal-to-noise degradation)
– Reflections (signal-to-noise degradation)
– Cross-talk and EMI (electromagnetic interference)
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Optical interconnect achieves higher bandwidth over
larger distances than Copper interconnect
– Also, components can be spread further apart without impacting
Bandwidth, which enables more efficient and cheaper cooling
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Motivation
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Optoelectronics (OE)
replaced Cu in long
(SONET) and short
(Enterprise) distances.
Extending OE to the
computer
- Box-to-Box
- Board-to-board
- Chip-to-chip
- On-chip?
May allow interconnects to
continue to scale in speed
However, cost should be
acceptable
- Comparable or less than
electrical
IEEE Spectrum, 2002
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High Speed I/O for Processors – Possible
Scenario
0-2 years
2-7 years
7+ years
Chip-2-Chip
(<20”)
Brd-2-Brd
(<30”, with 2
connectors)
Copper
Optical
Box-2-Box
(<3 meters, with 4
connectors & 3 cables)
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I/O Architecture Evolution - Optical I/O will be
necessary, but hard to predict it’s timing of introduction since
Electrical interconnect will continue to innovate
Optical
Interconnects?
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>12 Gb/s Copper Signaling
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Third Generation
I/O Architecture
1Gb/s Parallel Bus
Signaling
Rate
(Gb/s)
HL
PCIx
HT
AGPx
UP TO 66 Mb/s
R I/O
VESA
VL
8.33 Mb/s
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Full Serial
Point to point
Max Bandwidth/Pin
Scalable >10 Gb/s
Flexibility
Multiple market
segment
PCI
EISA
MCA
ISA
80’s
90’s
00’s
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CPU Platform Bandwidth History
(CPU interface and Memory)
Pentium® 4
CPU
CPU Core Freq
Pentium® II
CPU
Pentium® III
CPU
Pentium®
CPU
80486
80386
80286
RDRAM BW
10000.0
1000.0
Optical needed
@ 20Gb/s per link
1985
1990
1995
2000
64bit DDR333
64bit
SDRAM100/133
64bit
SDRAM PC66/100
64bit
DRAM
EDO
32bit
DRAM
32bit
DRAM
1.0
1980
16bit
DRAM
10.0
128bit DDR400
(40GB/s = 320Gb/s
16 pt-to-pt links)
100.0
8bit
DRAM
Bandwidth (MB/sec), CPU Core Freq (MHz)
100000.0
8088
CPU I/F and DRAM BW
2005
2010
Bandwidth growing exponentially and is expected to continue
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As Frequency increases, optical interconnect
Conversion Loss
Line Attenuation (dB)
Opticzl
attenuates much more slowly than electrical
Channel Bandwidth
Electrical attenuation
Optical attenuation
Optical attenuation
Signal-to-noise
increase
-55
Noise Floor
Frequency
Target Data Rate
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Summary of Key Points
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Circuit I/O architecture going from multi-drop bus to a
point-to-point bus for performance
Chip-to-Chip I/O speed will become limited by the Copper
board trace resistance / capacitance (attenuation vs
frequency)
Beyond ~20Gb/s may need to go to a non-copper board
interconnect – Optical waveguide.
Chip-to-Chip Optical Interconnect could be introduced
when it is faster/better/cheaper than electrical.
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Summary of Requirements for Optical Interconnect
for Chip-to-Chip I/O in Computing Systems
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Electronic
- High-speed (>20Gb/s), low power, CMOS circuits
Optical
- High-speed (>20Gb/s) Vertical Cavity Lasers (VCSEL)
and Photodiodes arrays
- Low loss, low cost, optical waveguides (polymer or other)
Packaging
- Hybrid Integration
- Compatible with IC industry
- Passive alignment
Low cost approach to testing
- Compatible with IC industry (in-line testing)
- Self-test circuits
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Key Results for the Optical I/O Technical Paper
at Photonics West 1/29/04
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Intel researchers built a fully functional chip-to-chip I/O link
working at 1-3 Giga-Transfers per second (GT/s).
8 Gb/s aggregate data rate (8 channels each at >1Gb/s)
demonstrated chip-to-chip over the optical link.
All the optical electronics (driver, receiver amplifier,
testing) built in Intel’s low cost 0.18um CMOS
All the assembly packaging based upon Intel’s high
volume OLGA BGA package
Optical elements are 1x12 linear array of GaAs PIN
detectors, GaAs Vertical Cavity Lasers (VCSEL), and
polymer waveguide.
Demonstrated at the system level with a complete
functional end-to-end link a highly integrated feasibility
prototpye
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Hybrid Integration Approach
Polymer Waveguides
•Key components
- CMOS Transceiver Chip
- 1x12 VCSELs, photodetector arrays
- 1x12 Polymer waveguide arrays
Transceiver chip
MT connector
VCSELs
Photodiodes
PCB
Schematic of Architecture
•Architecture Advantages:
- Parallel architecture increases
throughput
- Optical port removes distance
limitation between two chips
- Leverages microprocessor
packaging technology
MT connector
Waveguide
Photodiodes
VCSELs
Transceiver chip
Prototype
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Hybrid Integrated Optical I/O Component Status
PRBS DATA
PRBS DATA
CLOCK
3Gb/s Transmitter Optical Eye
1Gb/s Full-link Error-Free Transmission
Current System Results
• Transmitter demonstrated 3Gb/s open eye data transmission.
• >1Gb/s full-link error-free data transmission obtained.
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Summary:
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Intel has made significant progress demonstrating the
feasibility of optical chip-to-chip interconnect.
Optical chip-to-chip interconnect may offer a faster,
cheaper, better alternative to metal-based data buses
between CPU and it’s supporting chips
The demonstration was done with 0.18um-CMOS
transceiver, with on-chip drivers, amps, and self-test
features. The transceiver chip is integrated with the
optical emitters, detectors, and wave-guides in a
hybrid package
This announcement is a progress report from Intel’s
Component’s Research Lab. Intel has not made a
determination on product plans based upon these
results.
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For further information on Intel's silicon technology,
please visit the Silicon Showcase at
www.intel.com/research/silicon
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BACK-UP SLIDES
Computer I/O Architecture
CPU
PCI
Express
Graphics
Memory
Memory
Bridge
HDD
Serial
ATA
PCI
Gb
Ethernet*
I/O
Bridge
USB2.0
Add ins
LPC
Add ins
SIO
Add ins
PCI Express
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I/O architecture has moved to point to point
I/O Bandwidth requirements are likely to exceed more than >10x
in next 10 years
Optical I/O is consistent with this architectural direction
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Optical IO Architectures
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Two main approaches based upon levels of
Integration
– Hybrid/Heterogeneous Component Integration
External optical components packaged with the microprocessor
– On-Chip Integration
Full integration of optical components on logic process flow except CW
laser (optical power supply)
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This research work focuses on the
Heterogeneous/Hybrid approach
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