Transcript ECE 598 EP - Stanford University

Transient Thermal Response
• Transient Models
– Lumped: Tenbroek (1997), Rinaldi
(2001), Lin (2004)
– Introduce CTH usually with approximate
Green’s functions; heated volume is a
function of time (Joy, 1970)
Instantaneous T rise
T 
E Pt

C  cV
Due to very sharp heating
pulse t ‹‹ V2/3/
– Finite-Element methods
More general
Simplest (~ bulk Si FET)
P
 r 
T (r , t ) 
erfc 

2 kSi r
 2 t 
t
 r 2 
1
P(t ')
T (r , t ) 
exp 
 dV ' dt '
3/ 2 
3/ 2
8 cV ( ) 0 (t  t ')
 4 (t  t ') 
Temperature evolution anywhere (r,t) due to arbitrary heating
function P(0<t’<t) inside volume V (dV’  V) (Joy 1970)
Temperature evolution of a step-heated point
source into silicon half-plane (Mautry 1990)
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Instantaneous Temperature Rise
L
Instantaneous T rise
d
W
T 
E Pt

C cV
Due to very sharp heating
pulse t ‹‹ V2/3/
• Neglect convection & radiation
• Assuming lumped body
• Biot = hL/k << 1, internal
resistance and T variation
neglected, T(x) = T = const.
© 2010 Eric Pop, UIUC
 2T P ''' hA
c T


(T  T0 ) 
2
x
k kV
k t
ECE 598EP: Hot Chips
1/ 
2
Lumped Temperature Decay
L
W
T decay
d
T(t=0) = TH
T  (TH  T0 )e( hA/ cV )t
• After power input switched off
• Assuming lumped body
• RTH = 1/hA
• CTH = cV
 2T P ''' hA
c T


(T  T0 ) 
2
x
k kV
k t
• Time constant ~ RTHCTH
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Electrical and Mechanical Analogy
• Thermal capacitance (C = ρcV) normally spread over the
volume of the body
• When Biot << 1 we can lump capacitance into a single
“circuit element” (electrical or mechanical analogy)
There are no physical elements analogous
to mass or inductance in thermal systems
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Transient Edge (Face) Heating
When is only the surface of a body heated?
I.e. when is the depth dimension “infinite”?
 2T 1 T

2
x
 t
Note: Only heated surface B.C. is available
T  Tfire
Ti  Tfire
 x 
 erf 

2

t


Lienhard book, http://web.mit.edu/lienhard/www/ahtt.html
Also http://www.uh.edu/engines/epi1384.htm
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Transient Heating with Convective B.C.
• If body is “semi-infinite” there is
no length scale on which to build
the Biot number
• Replace Biot  (αt)1/2

 


  erf    exp    2 erfc    
2
2




T  T fire
Ti  T fire


x
t

h t
k
Note this reduces to previous slide’s simpler
expression (erf only) when h=0!
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Transient Lumped Spreading Resistance
Source: Timo Veijola, http://www.aplac.hut.fi/publications/bec-1996-01/bec/bec.html
1  2 (rT ) P 1 T
 
2
r r
k  t
• Point source of heat in material
with k, c and α = k/c
• Or spherical heat source, outside
sphere
~ Bulk Si FET transient
T (r , t ) 
P
 r 
erfc 

2 kSi r
 2 t 
Temperature evolution of a step-heated point
source into silicon half-plane (Mautry 1990)
• This is OK if we want to roughly
approximate transistor as a sphere
embedded in material with k, c
Characteristic diffusion length LD = (αt)1/2
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Transient of a Step-Heated Transistor
In general:
Carslaw and Jaeger (2e, 1986)
© 2010 Eric Pop, UIUC
“Instantaneously” means short pulse time
vs. Si diffusion time (t < LD2/α) or
short depth vs. Si diffusion length (L < (αt)1/2)
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Device Thermal Transients (3D)
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Temperature of Pulsed Diode
Holway, TED 27,
433 (1980)
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Interconnect Reliability
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Transient of a Step-Heated Interconnect
When to use “adiabatic
approximation” and
when to worry about
heat dissipation into
surrounding oxide
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Transient Thermal Failure
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Understanding the sqrt(t) Dependence
• Physical = think of the
heated volume as it
expands ~ (αt)1/2
• Mathematical = erf
approximation
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Time Scales of Thermal Device Failure
• Three time scales:
– “Small” failure times: all heat dissipated within defect, little
heat lost to surrounding ~ adiabatic (ΔT ~ Pt)
– Intermediate time: heating up surrounding layer of (αt)1/2
– “Long” failure time ~ steady-state, thermal equilibrium
established: ΔT ~ P*const. = PRTH
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Ex: Failure of SiGe HBT and Cu IC
Wunsch-Bell
curve of HBT
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Ex: Failure of Al/Cu Interconnects
Banerjee et al., IRPS 2000
Failed Interconnect
~ 12 mm
AlCu on polymer
Intel Corporation
Ju & Goodson, Elec. Dev. Lett. 18, 512 (1997)
Metal 4
• Fracture due to the
expansion of critical volume
of molten Al/Cu. (@ 1000 0C)
200 K
T along Interconnect
t = 200 ns
T
150 ns
100 ns
0
0
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Temperature Rise in Vias
S. Im, K. Banerjee, and K. E. Goodson, IRPS 2002
Via and interconnect dimensions are not consistent from a heat generation / thermal
resistance perspective, leading to hotspots. New model accounts for via conduction and Joule
heating and recommends dimensions considering temperature and EM lifetime.
15
ILD
10
o
Via
Metal Line
Hotspot
Tn-T0 [ C]
vias with
Joule heating
no vias
5
isothermal
vias
0
1
2
3
4
5
6
7
8
Metal Level (n)
Based on ITRS global lines of a 100 nm technology node
(Left: ANSYS simulation. Right: Closed-Form Modeling)
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Time Scales of Electrothermal Processes
IESD (A)
Source: K. Goodson
6
5
4
3
2
1
CDM
Governs total power
consumption, packagelevel cooling
HBM
-1
0
20
40
MM
60
80
gate
switching
Stress
Timescales
Mechanistic
Timescales
electron & phonon
relaxation times
10-11
Governs relative
importance of
failure modes for ESD
ESD / EOS Phenomena
clock
period
conduction processes within
transistor and gate oxide
10-12
© 2010 Eric Pop, UIUC
100 120ns
Governs peak transistor
temperature & mobility
reduction, leakage
augmentation
diffusion processes within
interconnects, vias, passivation
10-10
10-9
seconds
ECE 598EP: Hot Chips
10-8
10-7
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ESD: Electrostatic Discharge
J. Vinson & J. Liou, Proc. IEEE 86, 2 (1998)
• High-field damage
…
• High-current damage
• Thermal runaway
…
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Common ESD Models
Gate
J. Vinson & J. Liou, Proc. IEEE 86, 2 (1998)
Source
Drain
Combined, transient,
electro-thermal device models
Lumped: Human-Body Model (HBM)
Lumped: Machine Model (MM)
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Reliability
Source: M. Stan
• The Arrhenius Equation: MTF=A*exp(Ea/kBT)
•
•
•
•
•
MTF: mean time to failure at T
A: empirical constant
Ea: activation energy
kB: Boltzmann’s constant
T: absolute temperature
Ea = 1.1 eV
Ea = 0.7 eV
• Failure mechanisms:
•
•
•
•
•
•
Die metalization (Corrosion, Electromigration, Contact spiking)
Oxide (charge trapping, gate oxide breakdown, hot electrons)
Device (ionic contamination, second breakdown, surface-charge)
Die attach (fracture, thermal breakdown, adhesion fatigue)
Interconnect (wirebond failure, flip-chip joint failure)
Package (cracking, whisker and dendritic growth, lid seal failure)
• Most of the above increase with T (Arrhenius)
• Notable exception: hot electrons are worse at low temperatures
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Improved Reliability Analysis
M. Stan (2007), Van der Bosch, IEDM (2006)
t failure

0
1
e
kT (t )
E
 a
kT ( t )
dt  th  const
life consumption rate
© 2010 Eric Pop, UIUC
• There is NO “one size fits all” reliability
estimate approach
• Typical reliability lifetime estimates done
at worst-case temperature (e.g. 125 oC)
which is an OVERDESIGN
• Apply in a “lumped” fashion at the
granularity of microarchitecture units
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Combined Package Model
0.3 oC/W
Rtotal (ITRS 2003)
0.2
Tj – junction temperature
Tc – case temperature
0.1
Ts – heat sink temperature
0
Ta – ambient temperature
© 2010 Eric Pop, UIUC
2000
ECE 598EP: Hot Chips
Rheat sink
Steady-state:
3DIC
Rchip
2005
Multicore
2010
2015
2020
24
Thermal Design Summary
• Temperature affects performance, power, and reliability
• Architecture-level: conduction only
– Very crude approximation of convection as equivalent resistance
– Convection, in general: too complicated, need CFD!
•
•
•
•
Use compact models for package
Power density is key
Temporal, spatial variation are key
Hot spots drive thermal design
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