Transcript Project Name: Hybrid Architecture of DCT/DFT/Wavelet

EE 800
Project Name:
Hybrid Architecture of DCT/DFT/Wavelet Transform (HWT)
Md. Ashraful Islam
Samia Sharmin Shimu
Objective
Hardware implementation of Hybrid
Discrete cosine transform (DCT) / Discrete
Fourier Transform (DFT)/Wavelet
Transform (HWT) in single chip.
Motivation
1. Combine three different
transformation method in one
chip
2. Hardware saving
3. Less Power consumption
Methodology
1.
2.
3.
4.
The Algorithm of combining DCT/DFT/HWT is obtained
from the paper, Zhu Chen, Moon Ho Lee “On Fast
Hybrid Source Coding Design”, 2007 International
Symposium on Information Technology Convergence.
The coefficient matrix of DCT, DFT and Haar wavelet
are structured in similar pattern to share the common
block diagrams.
Different combination of matrix algorithm has been use
to decompose the classical DCT,DFT and Haar matrix
to find out the common blocks which will be shared by
the three filters in our architecture.
Hardware implementation would be done by Verilog.
Butterfly data flow diagram of N-by-N DCT II
Butterfly data flow diagram of N-by-N DFT
Butterfly data flow diagram of N-by-N HWT
Application
Signal and image processing, Video
data compression can be performed
by this hybrid chip using DCT/DFT/
HWT.
Question?
Thanks