Transcript Additional Features & Architecture of DTMROC DSM version

DSM DTMROC version for the ATLAS TRT
System Overview
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Chip Architecture
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Main Features
16 low level differential ternary (Transition/Tracking/”0”) current inputs
On-board DLL generates 8 equally (3.125ns) spaced clocks
Tracking / Transition pulses sampling at 3.125 / 25 ns
256 Pipeline locations = 6.25us latency (programmable)
128 Derandomizer locations = 42 events
Two 6-bit and six 8-bit linear DAC’s
Programmable Test Pulses and Threshold voltages for the analog front-end chips
Fast self-trigger - “Wire Or” of selected input channels
Internal voltage sensing
SEU detecting and resistant circuitry
JTAG Scan Chain, Boundary Scan and RAM BIST test
Detailed Status monitoring
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Ternary Input translator
Tri-level differential current pulses > 4ns wide
200µA current steps
– Transition Radiation
– Tracking pulse
– No signal
LHCC Colmar, France
September 9-13, 2002
- 0 µA
- 200 µA
- 400 µA
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DSM DTMROC version for the ATLAS TRT
DLL and Time-digitizer
DLL employs 32 elements
delay chain, phase
detector and a charge
pump
8 equally spaced clock
outputs used to sample
straw track pulses
50% duty cycle clock
output can be selected to
run the chip core logic
LHCC Colmar, France
September 9-13, 2002
REF CLOCK
BC1
BC2
BC3
BC4
BC5
BC6
BC7
BC8
Lthr
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00000011
Frontend Latching
11111110
Frontend Latching
In pipeline latching
In pipeline latching
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LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Pipeline and Derandomizer Implementation
Pipeline memory space is built of 34 parallel synchronous dualport SRAM banks of 1289-bit words. Total storage capacity is
256153-bit words. To avoid power consumption fluctuation, every
odd SRAM bank has been connected to a True address bus and
every even bank is driven by a Inverted address bus.
Derandomizer is acting as a FIFO. It is build of 17 parallel banks
of the same SRAM. Total storage capacity is 128153-bit words
(128/3 > 42 events).
Clock gating technique provides a power-efficient implementation
(Clock/Trigger rate = 40MHz/75KHz)
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Read-Out
Full/Reduced read-out : 444/380 bits per event, including Header
LVDS-compatible, tristate drivers -> 40 Mbits/s copper links
“Wire-OR” – self triggering
fast-out option. Selected
ternary inputs contribute
to the chip-level trigger.
When multiple DTMROC
are connected in parallel
the currents add.
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
DAC’s
Each of the DAC consists of 256 identical PMOS slave current
mirrors. Reference for the slave mirrors is provided by a current
mirror master consisting of 128 PMOS unit devices (L=8um,
W=5um)). The current mirror master is sandwiched between two
DACs.
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Testability (1)
A general-purpose Status Register was introduced to indicate the status of the
most important components of the DTMROC
Error bit representing the logical OR of all DTMROC error indicators is provided
in the header field of output data stream (substitution of the DLL status bit)
All internal registers are equipped with the parity check logic
In addition to the DLL lock bit, a “watch dog” and a “dynamic” check circuitries
examine the DLL outputs quality
JTAG Boundary-Scan is implemented as a serial shift register that is wrapped
around the boundary of the chip
Special scan mode allows performing the extended production tests of the
internal logic by configuring all DTMROC flip-flops as a large shift register
controlled via JTAG interface
Pipeline and Derandomizer memories are equipped with Build-In-Self-Test
(BIST) controlled via the Configuration register and JTAG interface
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Testability (2) - DLL control
“Static” DLL lock bit
“Watch dog” continuously compares rates of the external and
internal DLL clocks
“Dynamic” tester examines the positions of 8 DLL outputs relative
to the external clock
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Testability (3) - JTAG Logic Implementation
Supported instructions:
 BYPASS  EXTEST  SAMPLE  TEST  IDCODE  RUNBIST  SCAN_PATH_TEST ID CODE capture value:
 Manufacturer ID  Part Number  Version Number LHCC Colmar, France
September 9-13, 2002
11111
00000
00010
00100
00001
10000
01000
24
4535
3
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DSM DTMROC version for the ATLAS TRT
Single Event Upsets Robustness and Detection
All internal registers are equipped with parity error check
The most critical parts are
built of the SEU resistant
and self-recovering elements
based on triple logic with
majority vote
Statistics circuit monitors the
number of detected SEU’s
LHCC Colmar, France
September 9-13, 2002
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DSM DTMROC version for the ATLAS TRT
Power UP and External Reset circuit
LHCC Colmar, France
September 9-13, 2002
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DSM DTMROC version for the ATLAS TRT
Design Tools issues
A number of synthesis-layout
cycles were done to generate
design specific custom wire
load models based on
Synopsys
extracted parasitics and,
Library
Compiler
therefore, to predict postroute timing with appropriate
margins during RTL synthesis
ogy
nol
h
c
Te ibrary
L
Behavioral
Model
verilog
Synopsys
synthesis
LHCC Colmar, France
September 9-13, 2002
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sts
Place
&
Route
W
ire
Ta Lo
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e
Net
li
HyperExtract
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t
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DSM DTMROC version for the ATLAS TRT
Synopsys and Layout path delay estimations
Synopsys
Layout Path
Path Delay, ns Delay, ns
Path Endpoint
ShiftRegister_reg_1_/D
ShiftRegister_reg_7_/D
ShiftRegister_reg_3_/D
ShiftRegister_reg_5_/D
ShiftRegister_reg_4_/D
ShiftRegister_reg_6_/D
DeraReadAddress_reg_6_/D
ShiftRegister_reg_8_/D
ShiftRegister_reg_2_/D
ShiftRegister_reg_0_/D
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
11.42
10.68
10.08
10.01
9.88
9.77
9.73
10.04
9.37
9.22
12.55
11.26
10.68
10.76
10.58
10.42
9.92
10.61
10
10.01
Variance
ns
-1.13
-0.58
-0.6
-0.75
-0.7
-0.65
-0.19
-0.57
-0.63
-0.79
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DSM DTMROC version for the ATLAS TRT
Chip Layout
Die size
5.25.0mm²
LHCC Colmar, France
September 9-13, 2002
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DSM DTMROC version for the ATLAS TRT
Status
Submitted/fabricated in January/March 2002
850 chips tested on the mixed signal IMS Tester at CERN
5 process corner (85/92/100/115/125%) evaluated
79% Yield for 850 chips
Irradiation tolerance test at CEA Saclay Pagure facility in July 2002
SEU sensitivity evaluated at the CERN PS in July 2002
Test Beam at the CERN H8 in August-September 2002
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Wafer map with five Process Corners
Wafer size 8”, 350 µm
Die size 5.25.0 mm²
1017 useable dies
100 TQFP 1414 mm²
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Power consumption
Analog
and
Digital
Design
estimate
130mA
@ 2.5V
40MHz
LHCC Colmar, France
September 9-13, 2002
Process
Variation
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DSM DTMROC version for the ATLAS TRT
SRAM performance
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Time measurements
VDD = 2.5V
VDD = 2.0V
LHCC Colmar, France
September 9-13, 2002
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DSM DTMROC version for the ATLAS TRT
Total Ionizing Dose tolerance
Tested at CEA Saclay Pagure facility in July 2002
7 Mrad total dose / 1.33 MeV gamma radiation
~10% increase in the DAC’s output voltage after irradiation, no
DNL change
No variations in the power consumption and the chip performance
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
SEU sensitivity
Evaluated at the CERN PS irradiation facility in July 2002
Integrated fluence of 1.81014p/cm2 on 24GeV beam
SEU cross-section for a single D flip-flop in different internal
registers varies from 0.810-14 to 1.210-14 cm2
The impact of SEU’s in the vital components is suppressed by
self-recovering logic
Chip upsets resulting in spurious data affecting the event
fragments synchronization in the back-end electronics are not
excluded
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Test Beam Analyses
Measurements of track position-resolution and hit-efficiency using
the ASDBLR/DTMROC-S chip set were made at the CERN H8
test beam in August 2002.
Drift time accuracy for a typical straw (right). The track radial position
R versus drift-time dependence ”V” curve is also plotted (left).
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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DSM DTMROC version for the ATLAS TRT
Conclusions
A new version of the DTMROC designed in a deep sub-micron
process has been fabricated and demonstrated to function.
Extensive lab tests give a high overall yield.
The process corner impact on the chip performance was
examined.
The effectiveness of the radiation tolerant layout and design
architecture techniques are confirmed.
Exhaustive internal test features were beneficial in simplifying and
ensuring comprehensive design verification, high fault coverage
and throughput.
Final production is scheduled for Q1 of 2003
LHCC Colmar, France
September 9-13, 2002
Vladimir RYJOV
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