Transcript EECT 7327 - Data Converters

Data Converters
EECT 7327
DAC
DAC Architecture
–1–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
DAC Architecture
• Nyquist DAC architectures
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Binary-weighted DAC
Unit-element (thermometer-coded) DAC
Segmented DAC
Resistor-string, current-steering, charge-redistribution DACs
• Oversampling DAC
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Oversampling performed in digital domain (zero stuffing)
Digital noise shaping (ΣΔ modulator)
1-bit DAC can be used
Analog reconstruction/smoothing filter
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Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Binary-Weighted DAC
–3–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Binary-Weighted CR DAC
CP
Cu = unit capacitance
Vo
VX
8Cu
4Cu
2Cu
Cu
Cu
VR
b3
b2
b1
b0
•
Binary-weighted capacitor array → most efficient architecture
•
Bottom plate @ VR with bj = 1 and @ GND with bj = 0
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Binary-Weighted CR DAC
CP
Vo
VX
8Cu
4Cu
2Cu
Cu
Cu
VR
b3
b2
b1
b0
N b
 2N Cu 
  VR   N- j
Vo  
j
 C  2N C 
2
j

1
p
u


N


  bN j  2N j Cu 
j1
V
Vo  
N
 R
N j
 Cp  Cu   2 Cu 
j1


 N

  bN j  2N j Cu 
j1
V
 
R
Cp  2N Cu 




•
Cp → gain error (nonlinearity if Cp is nonlinear)
•
INL and DNL limited by capacitor array mismatch
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Stray-Insensitive CR DAC


2N Cu

Vo 
 N
Cp  2N1Cu  Cu
 2 Cu 
A



N
  V  bN- j
j
 R 
j1 2


16Cu
CP
Vo
VX
A
8Cu
4Cu
2Cu
Cu
Large A needed
to attenuate
summing-node
charge sharing
VR
b3
b2
b1
b0
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
MSB Transition
Code 0111
Code 1000




C

C

C
1
2
3
  VR
Vo  0111  
4


C
+
C
+
C

p
0
j


j=1






C
4
  VR
Vo 1000   
4


C
+
C
+
C

p
0
j


j=1


Assume: C4  C1  C2  C3   Cu  δC,
DNL  Vo 1000  Vo 0111  1LSB 1LSB

δC
C
Cu
 δC Cu
C

Largest DNL error occurs at the midpoint where MSB transitions, determined
by the mismatch between the MSB capacitor and the rest of the array.
–7–
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Midpoint DNL
δC < 0
δC > 0
Ao
Ao
+DNL
0
0111 1000
-DNL
0
Di
0111 1000
•
δC > 0 results in positive DNL
•
δC < 0 results in negative DNL or even nonmonotonicity
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Di
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Output Glitches
• Cause: Signal
and clock skew
in circuits
• Especially
severe at MSB
transition where
all bits are
switching –
Vo
0111…111 →
Time
1000…000
•
Glitches cause waveform distortion, spurs and elevated noise floors
•
High-speed DAC output is often followed by a de-glitching SHA
–9–
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
De-Glitching SHA
...
b1
DAC
SHA
Vo
bN
SHA samples the output
of the DAC after it settles
and then hold it for T,
removing the glitching
energy.
Vo
Time
SHA output must be smooth (exponential settling can be viewed as pulse
shaping → SHA BW does not have to be excessively large).
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Frequency Response
|H(f)|
SHA
ZOH
0
HZOH  jω  e
fs
j
ωT
2

2fs

sin ωT
ωT
2

3fs
HSHA  jω 
2
– 11 –
f
1
1 j ω
ω3dB
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Binary-Weighted Current DAC
N
Vo  IR  
j1
bN- j
2
R
j
VX
b3
b2
b1
b0
I/2
I/4
I/8
I/16
Vo
A
•
Current switching is simple and fast
•
Vo depends on Rout of current sources without op-amp
•
INL and DNL depend on matching, not inherently monotonic
•
Large component spread (2N-1:1)
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
R-2R DAC
N
bN- j
j1
2j
Vo  IR  
R
VX
b3
2R
b2
2R
I/2
R
b1
2R
I/4
Vo
b0
2R
I/8
R
R
A
I/16
2R
I
•
A binary-weighted current DAC
•
Component spread greatly reduced (2:1)
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Data Converters
EECT 7327
DAC
Unit-Element DAC
– 14 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Resistor-String DAC
Di
VR
b0 b0
b1 b1
3
2
1
Vo
0
Vo
•
Simple, inherently monotonic → good DNL performance
•
Complexity ↑ speed ↓ for large N, typically N ≤ 8 bits
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Code-Dependent Ro
VR
Di
b0 b0
b1 b1
Vo
Vo
Co
t
Signal-dependent
RoCo causes HD
Ro
•
Ro of ladder varies with signal (code)
•
On-resistance of switches depend on tap voltage
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
DNL
R+ΔR1 R+ΔR2
V1
V2
VN
j1
Vj 
...
R+ΔRN-1 R+ΔRN
R
j1
k
1
N
R
1
VN+1
k
 VR 
 j  1R   ΔRk
1
N
NR   ΔRk
j2
 VR
Vj-1 
1
Vj  Vj-1 
ΔR  0, σR 
VR
 j  2R   ΔRk
1
N
NR   ΔRk
1
R  ΔR j1
N
NR   ΔRk
VR ΔR j1
 VR 

 VR
N
NR
1
V  VR ΔR j1

DNL j   Vj  Vj-1  R 

N N
R

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 DNL  0, σDNL 
σR
R
 VR
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
INL
j1
Vj 
R
k
1
N
R
1
j1
j1
k
 VR 
 j  1 R   ΔRk
1
N
NR   ΔRk
 VR 
j 1
VR 
N
N
N - j  1 ΔRk   j  1 ΔRk
1
j
2
NR
1
j  1 N - j  1 σR 2 2

j 1
2
 Vj 
VR , σ Vj 
VR
3
2
N
N
R
1 σR 2 2
N
N
2
 σ Vj  max  
V
,
when
j


1

R
4N R2
2
2
j -1  VR

INL j   Vj 
VR 
N

 N
 INL  0, σINL max  
– 18 –
N  σR 


2 R
VR
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
INL and DNL of BW DAC
A BW DAC is typically constructed using unit elements, the same way as
that of a UE DAC, for good component matching accuracy.
INL  0, σINL  max  

N  σR 


2 R 
σ 
DNL  0, σDNL  max   2  INL  N  R 
R 
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Current-Steering DAC
…
…
Io
…
…
I
I
I
Binary-to-Thermometer Decoder
...
b1
bN
•
Fast, inherently monotonic → good DNL performance
•
Complexity increases for large N, requires B2T decoder
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Unit Current Cell
Io
...
Φ
bN
...
ROW/COL
Decoder
Sj
Sj
Φ
b1
I
•
2N current cells typically decomposed into a (2N/2×2N/2) matrix
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Current source cascoded to improve accuracy (Ro effect)
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Coupled inverters improve synchronization of current switches
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Data Converters
EECT 7327
DAC
Segmented DAC
– 22 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
BW vs. UE DACs
Binary-weighted DAC
Unit-element DAC
•
•
Pros
– Min. # of switched elements
– Simple and fast
– Compact and efficient
•
– Good DNL, small glitches
– Linear glitch energy
– Guaranteed monotonic
•
Cons
– Large DNL and glitches
– Monotonicity not guaranteed
•
Pros
Cons
– Needs B2T decoder
– complex for N ≥ 8
•
INL/DNL
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ 2*INL
INL/DNL
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ σ
Combine BW and UE architectures → Segmentation
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Segmented DAC
VFS
• MSB DAC: Mbit UE DAC
…
• LSB DAC: L-bit
BW DAC
• Resolution: N =
M+L
Vo
MSB’s
• 2M+L switching
elements
• Good DNL
• Small glitches
LSB’s
• Same INL as
BW or UE
0
0
2N-1
Di
– 24 –
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Comparison
Example: N = 12, M = 8, L= 4, σ = 1%
Architecture
σINL
σDNL
# of s.e.
Unit-element
0.32 LSB’s
0.01 LSB’s
2N = 4096
Binary-weighted
0.32 LSB’s
0.64 LSB’s
N = 12
Segmented
0.32 LSB’s
0.06 LSB’s
2M+L = 260
Max. DNL error occurs at the transitions of MSB segments
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Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
Example: “8+2” Segmented Current DAC
Ref: C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm2,” IEEE
Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
– 26 –
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
MSB-DAC Biasing Scheme
Common-centroid global biasing + divided 4 quadrants of current cells
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Data Converters
EECT 7327
DAC
MSB-DAC Biasing Scheme
– 28 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Randomization and Dummies
– 29 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
DAC
Professor Y. Chiu
Fall 2014
References
1.
2.
3.
4.
5.
6.
7.
8.
9.
M. J. M. Pelgrom, JSSC, pp. 1347-1352, issue 6, 1990.
D. K. Su and B. A. Wooley, JSSC, pp. 1224-1233, issue 12, 1993.
C.-H. Lin and K. Bult, JSSC, pp. 1948-1958, issue 12, 1998.
K. Khanoyan, F. Behbahani, A. A. Abidi, VLSI, 1999, pp. 73-76.
K. Falakshahi, C.-K. Yang, B. A. Wooley, JSSC, pp. 607-615, issue 5, 1999.
G. A. M. Van Der Plas et al., JSSC, pp. 1708-1718, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1719-1732, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1841-1852, issue 12, 2000.
A. van den Bosch et al., JSSC, pp. 315-324, issue 3, 2001.
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