Transcript Chapter 1

The state in a stored-program digital computer
FF.. FF16
instructions
registers
address
dat a
processor
instructions
and data
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memory
00. .0016
The transistor circuit of a static 2-input CMOS
NAND gate
Vdd
A
A.B
B
Vss
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The logic symbol and truth table for a NAND gate
A
B
out put
Logic sy mbol
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A
B
Output
0
0
1
0
1
1
1
0
1
1
1
0
Truth table
The MU0 instruction format
4 bits
opc ode
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12 bits
S
The MU0 instruction set
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Instruction
Opcode
Effect
LDA S
0000
ACC := mem 16[S]
STO S
0001
mem 16[S] := ACC
ADD S
0010
ACC := ACC + mem 16[S]
SUB S
0011
ACC := ACC - mem 16[S]
JMP S
0100
PC := S
JGE S
0101
if ACC >= 0 PC := S
JNE S
0110
if ACC !=0 PC := S
STP
0111
stop
MU0 datapath example
address bus
PC
control
IR
memory
ALU
ACC
data bus
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MU0 register
transfer level
organization
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MU0 control logic
In p ut s
Op c o de Ex / f t ACC1 5
In s t ruc t i o n
Re s e t ACCz
Reset
xxxx
1
x
x
x
LDA S
0000
0
0
x
x
0000
0
1
x
x
STO S
0001
0
0
x
x
0001
0
1
x
x
ADD S
0010
0
0
x
x
0010
0
1
x
x
SUB S
0011
0
0
x
x
0011
0
1
x
x
JMP S
0100
0
x
x
x
JGE S
0101
0
x
x
0
0101
0
x
x
1
JNE S
0110
0
x
0
x
0110
0
x
1
x
STOP
0111
0
x
x
x
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Out p ut s
Bs el
PCc e ACCo e
MEMrq Ex / f t
As e l ACCc e IRc e
ALUf s
Rn W
0
0
1
1
1
0
=0
1
1
0
1
1
1
0
0
0
=B
1
1
1
0
0
0
1
1
0
B+1
1
1
0
1
x
0
0
0
1
x
1
0
1
0
0
0
1
1
0
B+1
1
1
0
1
1
1
0
0
0
A+B
1
1
1
0
0
0
1
1
0
B+1
1
1
0
1
1
1
0
0
0
A-B
1
1
1
0
0
0
1
1
0
B+1
1
1
0
1
0
0
1
1
0
B+1
1
1
0
1
0
0
1
1
0
B+1
1
1
0
0
0
0
1
1
0
B+1
1
1
0
1
0
0
1
1
0
B+1
1
1
0
0
0
0
1
1
0
B+1
1
1
0
1
x
0
0
0
0
x
0
1
0
MU0 ALU logic for one bit
Binv
Cin
reset
sum
B
A
Aen
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Cout
A 4-address instruction format
f bits
n bits
f unc tion op 1 addr.
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n bits
op 2 addr.
n bits
n bits
des t. addr. nex t_i addr.
A 3-address instruction format
f bits
n bits
f unc tion op 1 addr.
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n bits
op 2 addr.
n bits
des t. addr.
A 2-address instruction format
f bits
n bits
f unct ion op 1 addr.
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n bits
des t. addr.
A 1-address (accumulator) instruction format
f bits
n bits
f unction op 1 addr.
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A 0-address instruction format
f bits
f unc tion
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Typical dynamic instruction usage
Instruction type
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Dynamic usage
Data movement
Control flow
43%
23%
Arithmetic operations
15%
Comparisons
13%
Logical operations
5%
Other
1%
Pipelined instruction execution
1
f et ch dec
2
3
ins truc tion
reg
f et ch dec
ALU mem res
reg
f et ch dec
ALU mem res
reg
ALU mem res
time
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Read-after-write pipeline hazard
1
f et ch dec
reg
f et ch dec
2
ALU mem res
stall
reg
ALU mem res
instruction
time
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Pipelined branch behaviour
1 (branch) f et ch dec
reg
f et ch dec
2
ALU mem res
reg
f et ch dec
3
ALU mem res
reg
f et ch dec
4
5 (br anch tar get)
ALU mem res
reg
f et ch dec
ALU mem res
reg
instruction
time
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ALU mem res