Transcript Address-Event Representation in Wireless Sensor Networks

An Energy Efficiency Evaluation for Sensor
Nodes with Multiple Processors, Radios and
Sensors
Deokwoo Jung
[email protected]
Embedded Networks and Applications Lab (ENALAB)
Yale University
*Research sponsored by NSF
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Challenges for designing energy efficient
wireless sensor network
Large set of Application domain
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From a simple data logging to a complex signal processing
Long sleep period
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For surveillance application, typically more than 90 % of lifetime is in
a sleep state
Dynamic roles
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A sensor node can perform various functionalities from a cluster head
to a simple end node
A large dynamic range of trade-off between power and performance
The fundamental limit of electronics in single type of hardware
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CPU Trend
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Computation cost of 32bit-FFT and energy efficiency
comparison in CPUs
10000
32-bit 416Mhz PXA271 CPU
16-bit 8Mhz MSP430 CPU
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100
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Computation
Efficiency (uJ/bit)
Sleep power(uW)
Wakeup overhead
(uJ)
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Radio Trend
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Data transfer cost of and energy efficiency comparison in
Radios
10000
802.11b-SMC2532
802.15.4-CC2420
1000
100
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Data Transfer
Efficiency (nJ/bit)
Listening power (mW)
Wakeup overhead
(uJ)
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Energy Trade-off in different roles
Large dynamic range of operation
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Collect and Forward
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Processing and Report
Computation Load
Communication Load
Average power consumption (mW)
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6
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Data Collecting Ceter
Processing Ceter
=1/1min
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3
low-end CPU+ high-end radios
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Data size (byte)
0
2000
4000
6000
8000
10000
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Related work for energy optimization
Energy-Efficient Platform
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Telos [Berkley], ZN1[HITACHI], Stargate[Crossbow], mPlatform [MS],
LEAP[UCLA], ASPIRE [Yale-UCLA-UMASS]
Energy-Aware Wireless Communication
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LEACH: Energy-efficient communication protocol for wireless sensor networks
[Heinzelman00]
S-MAC: An Energy-Efficient MAC Protocol for Wireless Sensor Networks[Wei02]
A MAC protocol to reduce sensor network energy consumption using a wakeup
radio.[Matthew05]
Network-Wide Energy Optimization
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SPAN: An energy-efficient coordination algorithm for topology maintenance in ad
hoc wireless networks [chan01]
GAF: Geography-informed energy conservation for ad hoc routing, [Chu01]
STEM: Topology management for energy efficient sensor networks[Curt02]
Cross-Layer Design and Optimization
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Cross-layer design for lifetime maximization in interference-limited wireless
sensor networks [Madan05]
Physical layer driven protocol and algorithm design for energy-efficient wireless
sensor networks [Eugene01]
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Our contribution
Reconfigurable platforms - high & low-end components in one
platform
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A large dynamic range of energy and performance trade-off
Using the most efficient component subset for each task
Its energy efficiency modeling has not been studied well
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Energy efficiency gain given a hardware set?
Parameters of affecting energy efficiency?
Optimal operation points given workload?
Sensor
Motion
Camera
Sensor
CPU
PXA271
TI MSP
Radio
802.15.4 802.11
CC2420 5006XS
Inter – Component Communication Link
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Analytical Model of Evaluating
Reconfigurable platform
Main design consideration factors
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Component Interconnect => Combination of each
component
The choice of hardware => Lifetime bound
Predicting energy behavior is a key step toward
optimum reconfigurable platform design
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Quantifying energy efficiency
Estimating energy efficiency gain
Identifying key parameters for energy efficiency
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Reconfigurable sensor platforms
Dual-Platform with Serial Interface
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Straight-forward SERIAL design between high-end and low-end platform
Limited binding among system components
Lowest interconnect protocol overhead -> Lowest latency
Limited Bandwidth (< 3.4 Mbps at I2C in High Speed mode)
Control
Control
Flash
Flash
SDRAM
SDRAM
MIF
Low-End Radio
(802.15.4)
RIF
Low-End CPU
(TI MSP)
RIF
IO
CIF
High-End CPU
(PXA271)
CIF
IO
RIF
High-End Radio
(802.11)
RIF
MUX
Voltage Regulator
Real Time Clock
MIF
Low-End Sensor
(Motion Sensor)
High-End Sensor
(Camera)
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Reconfigurable sensor platforms
Reconfigurable Platform with reconfigurable interconnect
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Maximum Reconfigurability, Complexity, and Power
Smallest latency and highest throughput.
Maximum range of power mode -> Fine-grained power control
Voltage Regulator
Low-End Sensor
(Motion Sensor)
High-End Sensor
(Camera)
Real Time Clock
Inter Component
Router
IO
MIF
Flash
SDRAM
Low-End Radio
(802.15.4)
Component Power control
Reconfigurable Interconnect
RIF-1
RIF-1
IO
IO IO
MIF
Shared RAM
and Arbiter
RIF-2
Flash
SDRAM
MIF
Low-End CPU
(TI MSP)
IO
MIF
High-End CPU
(PXA271)
IO
RIF-2
High-End Radio
(802.11)
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Architecture abstraction
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It’s all about path combination…
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Model Sensor Operation as a SemiMarkov Decision Chain
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P1  1, A1  l, o
Preprocessing
Stage
S0
Trigger-Driven Energy
Management Model
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Power mode, time variable, and
transition cost of current state are
determined previous decision
action A, e.g {l,h}={Low-end CPU,
High-end radio }
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Embedded chain in processing
stage and communication stage
characterizes workload profile in
each stage.
Processing
Stage
S1
P2  0.2, A2  o, o
P3  0.8, A3  l, h
P4  1, A4  o, o
Comm.
Stage
S2
L
H
O
Using Low-End
Using High-End
Off
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An Energy Efficiency Evaluation for Sensor Nodes with
Multiple Processors, Radios and Sensors
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Closed form Energy Efficiency Formula
Solving Bellman equation derived from semi Markov decision process
Decision vectors of
CPU and radios
Function of Uk
(Arrival rate, Proc.time in low-end CPU, Proc.time in high end CPU,
Comm.time in low-end Radios, Comm.time in high end Radios,
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An Energy Efficiency Evaluation for Sensor Nodes with
Multiple Processors, Radios and Sensors
Graphical Analysis Example of Energy Efficiency evaluation
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simple low/high-end node and architecture with dynamic interconnect
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δ
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An Energy Efficiency Model Verification
Using LEAP node Architecture*
(*) The low power energy aware processing (LEAP)
embedded networked sensor system. In IPSN ’06
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An Energy Efficiency Evaluation for Sensor Nodes with
Multiple Processors, Radios and Sensors
Simulation result – Optimal Average Power Consumption
Optimal Average
Power Consumption
g* (mW)
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Low-End Node
Reconf. Interconnect
Static Interconnect
3
2
1
0
Energy Efficiency Ratios
sl
rl
rs
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5
10
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4
2
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Opt.Avg.Power with dynamic
Opt.Avg.Power with Low - ends
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Opt.Avg.Power with Static
Opt.Avg.Power with Low - ends
500
1000
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Opt.Avg.Power with dynamic
Opt.Avg.Power with Static
500
1000
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2000
Iteration
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An Energy Efficiency Evaluation for Sensor Nodes with
Multiple Processors, Radios and Sensors
Simulation result – Upper Bound of Energy Efficiency Gain
100
50
l
g* (mW)
Low-End Node
0
0
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Upper Bound
400
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1000
1200
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1000
1200
1400
Simulation
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0
0
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Upper Bound
Simulation
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r
Average Optimal
Energy Efficiency Gain Power Consumption
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20
0
0
200
400
600
Iteration
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How much can we afford to spend on the
interconnect ?
Numerical result – Interconnect Chip Power Budget
Dynamic Range of
Power Mode in Platform  = 1/5min,  = 5.06
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 = 1/5min,  = 6.06
 = 1/1hr,  = 6.27
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Energy Efficiency Gain, 
r
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Opt.Avg.Power with dynamicinterconnect
Opt.Avg.Power with low - end nodes
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δ=6.06
2
>2x
1
0
0
δ=5.06
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500
Interconnect Chip Power, PInC (mW)
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Conclusion and Future work
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Follow the guideline before you build!
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Energy efficiency evaluation model of Reconfigurable platform
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Framework to pursue a design flow for sensor platform with
multiple sensors, CPUs, and radios.
Opportunity in designing an interconnect chip – Might improve its
energy efficiency by 8 X
Design target for Interconnect chip: Power consumption bound,
event arrival rate, dynamic range of power
Reconfiguration algorithms and Simulation
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Online estimation of system parameter
Optimal online reconfiguration algorithm
Simulation for proposed reconfiguration algorithms
* For More information pleas, visit “http://www.eng.yale.edu/enalab/aspire.htm”
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