Transcript Introduction to Computer Systems

Virtual Memory (I)
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Outline
•
•
•
•
•
•
Physical and Virtual Addressing
Address Spaces
VM as a Tool for Caching
VM as a Tool for Memory Management
VM as a Tool for Memory Protection
Suggested reading: 9.1~9.5
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Physical Addressing
• Attributes of the main memory
– Organized as an array of M contiguous byte-sized
cells
– Each byte has a unique physical address (PA)
started from 0
• physical addressing
– A CPU use physical addresses to access memory
• Examples
– Early PCs, DSP, embedded microcontrollers, and
Cray supercomputers
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A System Using Physical Addressing
CPU
Physical address
(PA)
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Main memory
0:
1:
2:
3:
4:
5:
6:
7:
8:
...
M-1:
Data word
• Used in “simple” systems like embedded microcontrollers
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in devices like cars, elevators, and digital picture frames
Virtual Addressing
• Virtual addressing
– the CPU accesses main memory by a virtual address
(VA)
• The virtual address is converted to the appropriate
physical address
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Virtual Addressing
• Address translation
– Converting a virtual address to a physical address
– Requires close cooperation between the CPU
hardware and the operating system
• HW: the memory management unit (MMU)
– Dedicated hardware on the CPU chip to translate
virtual addresses on the fly
• SW: A look-up table
– Stored in main memory
– Contents are managed by the operating system
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A System Using Virtual Addressing
CPU Chip
CPU
Virtual address
(VA)
4100
MMU
Physical address
(PA)
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Main memory
0:
1:
2:
3:
4:
5:
6:
7:
8:
...
M-1:
Data word
• Used in all modern servers, desktops, and laptops
• One of the great ideas in computer science
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Address Space
• Address Space
– An ordered set of nonnegative integer addresses
• Linear Space
– The integers in the address space are consecutive
• N-bit address space
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Address Spaces
Linear address space: Ordered set of contiguous non-negative
integer addresses:
{0, 1, 2, 3 … }
Virtual address space: Set of N = 2n virtual addresses
{0, 1, 2, 3, …, N-1}
Physical address space: Set of M = 2m physical addresses
{0, 1, 2, 3, …, M-1}
•Clean distinction between data (bytes) and their
attributes (addresses)
•Each object can now have multiple addresses
•Every byte in main memory:
one physical address, one (or more) virtual addresses
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Address Space
• K=210(Kilo), M=220(Mega), G=230(Giga),
T=240(Tera), P=250(Peta), E=260(Exa)
#virtual address
bits (n)
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16
32
48
64
#virtual address
(N)
256
64K
4G
256T
16E
Largest possible
virtual address
255
64K-1
4G-1
256T-1
16E-1
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Why Virtual Memory (VM)?
• Uses main memory efficiently
– Use DRAM as a cache for the parts of a virtual
address space
• Simplifies memory management
– Each process gets the same uniform linear address
space
• Isolates address spaces
– One process can’t interfere with another’s memory
– User program cannot access privileged kernel
information
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Using Main Memory as a Cache
SRAM
DRAM
Disk
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Using Main Memory as a Cache
• DRAM vs. disk is more extreme than SRAM vs.
DRAM
– Access latencies:
• DRAM ~10X slower than SRAM
• Disk ~100,000X slower than DRAM
– Bottom line:
• Design decisions made for DRAM caches driven by
enormous cost of misses
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Design Considerations
• Line size?
– Large, since disk better at transferring large
blocks
• Associativity?
– Full, to minimize miss rate
• Write through or write back?
– Write back, since can’t afford to perform small
writes to disk
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Page
• Virtual memory
– Organized as an array of contiguous byte-sized
cells stored on disk conceptually.
– Each byte has a unique virtual address that serves
as an index into the array
– The contents of the array on disk are cached in
main memory
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Page
• The data on disk is partitioned into blocks
– Serve as the transfer units between the disk and
the main memory
Virtual memory
– virtual pages (VPs)
VP 0 Unallocated
VP 1 Cached
– physical pages (PPs)
• or page frames
VP 2n-p-1
Uncached
Unallocated
Cached
Uncached
Cached
Uncached
Physical memory
0
0
Empty
PP 0
PP 1
Empty
Empty
PP 2m-p-1
M-1
N-1
Virtual pages (VPs)
stored on disk
Physical pages (PPs)
cached in DRAM
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Page Attributes
• Unallocated:
– Pages that have not yet been allocated (or created)
by the VM system
– Do not have any data associated with them
– Do not occupy any space on disk.
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Page Attributes
• Cached:
– Allocated pages that are currently cached in
physical memory.
• Uncached:
– Allocated pages that are not cached in physical
memory.
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Page Table
• Each allocate page of virtual memory has
entry in page table
• Mapping from virtual pages to physical pages
– From uncached form to cached form
• Page table entry even if page not in memory
– Specifies disk address
• OS retrieves information
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Page Table
“Cache”
Page Table
Location
Data
Object Name
D:
0
0:
243
X
J:
On Disk
1:
17
•
•
•
N-1:
105
•
•
•
X:
1
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Page Table
Memory resident
page table
Virtual Page
Number
Valid
PTE0
PTE9
1
1
0
0
1
1
0
1
0
1
(physical page
or disk address)
Physical Memory
VP4
PP0
VP1
PP5
NULL
Disk Storage
(swap file or
regular file system file)
VP2
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Page Hits
Memory
0:
1:
Page Table
Virtual
Addresses
0:
1:
Physical
Addresses
CPU
P-1:
N-1:
Disk
Address Translation: Hardware converts virtual addresses to
physical addresses via an OS-managed lookup table (page table)
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Page Faults
• Page table entry indicates virtual address not
in memory
• OS exception handler invoked to move data
from disk into memory
– current process suspends, others can resume
– OS has full control over placement, etc.
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Page Faults
• Swapping or paging
• Swapped out or paged out
• Demand paging
Before fault
After fault
Memory
Memory
Page Table
Virtual
Addresses
Physical
Addresses
CPU
Page Table
Virtual
Addresses
Physical
Addresses
CPU
Disk
Disk
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Servicing a Page Fault
• Processor Signals
Controller
– Read block of length P
starting at disk address
X and store starting at
memory address Y
(1) Initiate Block Read
Processor
Reg
Cache
Memory-I/O bus
Memory
I/O
controller
disk
Disk
disk
Disk
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Servicing a Page Fault
• Read Occurs
– Direct Memory
Access (DMA)
– Under control
of I/O
controller
Processor
Reg
Cache
Memory-I/O bus
(2) DMA Transfer
Memory
I/O
controller
disk
Disk
disk
Disk
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Servicing a Page Fault
• I / O Controller
Signals Completion
– Interrupt processor
– OS resumes
suspended process
Processor
Reg
(3) Read
Done
Cache
Memory-I/O bus
Memory
I/O
controller
disk
Disk
disk
Disk
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Locality to the Rescue Again!
• Virtual memory works because of locality
• At any point in time, programs tend to access
a set of active virtual pages called the
working set
– Programs with better temporal locality will have
smaller working sets
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Locality to the Rescue Again!
• If (working set size < main memory size)
– Good performance for one process after
compulsory misses
• If ( SUM(working set sizes) > main memory
size )
– Thrashing: Performance meltdown where pages
are swapped (copied) in and out continuously
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Why Virtual Memory (VM)?
• Uses main memory efficiently
– Use DRAM as a cache for the parts of a virtual
address space
• Simplifies memory management
– Each process gets the same uniform linear address
space
• Isolates address spaces
– One process can’t interfere with another’s memory
– User program cannot access privileged kernel
information
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VM as a Tool for Memory Management
• Key idea: each process has its own virtual
address space
– It can view memory as a simple linear array
Virtual
Address
Space for
Process 1:
0
0
VP 1
VP 2
N-1
Virtual
Address
Space for
Process 2:
PP 2
...
Address
translation
PP 6
0
(e.g., read-only
library code)
PP 8
VP 1
VP 2
...
...
N-1
Physical
Address
Space
(DRAM)
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M-1
VM as a Tool for Memory Management
• Memory allocation
– Each virtual page can be mapped to any physical page
– A virtual page can be stored in different physical
pages at different times
Virtual
Address
Space for
Process 1:
0
0
VP 1
VP 2
N-1
Virtual
Address
Space for
Process 2:
PP 2
...
Address
translation
PP 6
0
(e.g., read-only
library code)
PP 8
VP 1
VP 2
...
...
N-1
Physical
Address
Space
(DRAM)
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M-1
VM as a Tool for Memory Management
• Sharing code and data among processes
– Map virtual pages to the same physical page
(e.g. PP 6)
Virtual
Address
Space for
Process 1:
0
0
VP 1
VP 2
N-1
Virtual
Address
Space for
Process 2:
PP 2
...
Address
translation
PP 6
0
(e.g., read-only
library code)
PP 8
VP 1
VP 2
...
...
N-1
Physical
Address
Space
(DRAM)
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M-1
Simplifying Linking and Loading
Kernel virtual memory
• Linking
0xc0000000
– Each program has
similar virtual address
space
0x40000000
– Code, stack, and
shared libraries
always start at the
same address
User stack
(created at runtime)
%esp
(stack
pointer)
Memory-mapped region for
shared libraries
brk
Run-time heap
(created by malloc)
Read/write segment
(.data, .bss)
Read-only segment
(.init, .text, .rodata)
0x08048000
0
Memory
invisible to
user code
Unused
Loaded
from
the
executable
file
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Simplifying Linking and Loading
Kernel virtual memory
• Loading
0xc0000000
– execve() allocates
virtual pages for .text
and .data sections
= creates PTEs
0x40000000
marked as invalid
– The .text and .data
sections are copied,
page by page, on
demand by the virtual
memory system
User stack
(created at runtime)
%esp
(stack
pointer)
Memory-mapped region for
shared libraries
brk
Run-time heap
(created by malloc)
Read/write segment
(.data, .bss)
Read-only segment
(.init, .text, .rodata)
0x08048000
0
Memory
invisible to
user code
Unused
Loaded
from
the
executable
file
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Why Virtual Memory (VM)?
• Uses main memory efficiently
– Use DRAM as a cache for the parts of a virtual
address space
• Simplifies memory management
– Each process gets the same uniform linear address
space
• Isolates address spaces
– One process can’t interfere with another’s memory
– User program cannot access privileged kernel
information
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VM as a Tool for Memory Protection
• Extend PTEs with permission bits
– The same physical page has different permission
for different process
SUP
Process i:
READ WRITE
Address
VP 0:
No
Yes
No
PP 6
VP 1:
No
Yes
Yes
PP 4
VP 2:
Yes
Yes
Yes
•
•
•
PP 2
Physical
Address Space
PP 2
PP 4
PP 6
SUP
Process j:
READ WRITE
Address
VP 0:
No
Yes
No
PP 9
VP 1:
Yes
Yes
Yes
PP 6
VP 2:
No
Yes
Yes
PP 11
PP 8
PP 9
PP 11
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VM as a Tool for Memory Protection
• Page fault handler checks these before
remapping
– If violated, send process SIGSEGV (segmentation
fault)
Physical
SUP
Process i:
READ WRITE
Address
VP 0:
No
Yes
No
PP 6
VP 1:
No
Yes
Yes
PP 4
VP 2:
Yes
Yes
Yes
•
•
•
PP 2
Address Space
PP 2
PP 4
PP 6
SUP
Process j:
READ WRITE
Address
VP 0:
No
Yes
No
PP 9
VP 1:
Yes
Yes
Yes
PP 6
VP 2:
No
Yes
Yes
PP 11
PP 8
PP 9
PP 11
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Next
• Address translation
• Accelerating translation
– with a TLB
– Multilevel page tables
• Suggested reading: 10.6
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