Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice Hall, Saint/McGrawHill, Weste/Addison Wesley]

Lecture 03: CMOS fabrication http://www.appliedmaterials.com/HTMAC/animated.html

Fabricating one transistor UV light Mask oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist exposed photoresist Photoresist Coating Mask-Wafer Alignment and Exposure Exposed Photoresist oxide Photoresist Develop Ionized CF 4 gas photoresist oxide Ionized oxygen gas oxide Oxide Etch Scanning ion beam ox S G D Ion Implantation Photoresist Remove S G D Active Regions oxygen gate oxide Oxidation (Gate oxide) silicon nitride S top nitride G D Nitride Deposition Dopant gas Silane gas polysilicon Polysilicon Deposition Contact holes S G D Contact Etch Ionized CCl 4 gas oxide Polysilicon Mask and Etch Metal contacts

drain

S G D Metal Deposition and Etch

Top view Polysilicon SiO2 Source Gate Drain p+ n p+ bulk Si Source Gate Drain Polysilicon SiO2 n+ p n+ bulk Si

Wafer preparation

Start with P substrate

1. Spin Resist Coating

2. Expose N Well Mask

3. Develop resist

4. Implant N Well

5. Remove Resist

Anneal wafer to diffuses N well (heal lattice) and grow new oxide layer

Remove oxide from anneal

1. Spin Resist

2. Expose resist with active diffusion mask

3. Develop resist

4. Grow oxide on exposed surface

5. Strip resist

Grown thin oxide over silicon surfaces

1. Deposit poly using Chemical Vapor Deposition (CVD)

2. Spin resist 3. expose resist using the GATE mask 4. develop resist 5. etch poly

Remove thin oxide layer where exposed

1. Spin resist 2. expose with P implant mask 3. develop resist 4. implant P 5. strip resist

1. Spin resist 2. expose with N implant mask 3. develop resist 4. implant N 5. strip resist

Remove resist – anneal wafer – oxide etch

Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4. etch contacts 5. strip resist

1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4. develop resist 5. etch metal 6. strip resist

Rest of metal layers follow similarly

Printing masks

The printer

Reticle library (SMIF pod interface) Operator console Illuminator optics Excimer laser (193 nm ArF ) Beam line Wafer transport system Reticle stage Wafer stage Auto-alignment system 4:1 Reduction lens NA = 0.45 to 0.6

Photolithography is used to print desired patterns on the wafer

UV light Reticle field size 20 mm × 15mm, 4 die per field 5:1 reduction lens masks Serpentine stepping pattern Image exposure on wafer 1/5 of reticle field 4 mm × 3 mm, 4 die per exposure Wafer The feature size directly depends on the wavelength of your lithographic system

Cross section of a 7-metal layer IC Next time: How to print different gates?