Transcript Chapter Five

Chapter Five
The Processor: Datapath and Control
1998 Morgan Kaufmann Publishers
1
Building the Datapath
•
Use multiplexors to stitch them together
PCSrc
M
u
x
Add
Add ALU
result
4
Shift
left 2
Registers
PC
Read
address
Instruction
Instruction
memory
Read
register 1
Read
Read
data 1
register 2
Write
register
Write
data
RegWrite
16
ALUSrc
Read
data 2
Sign
extend
M
u
x
3 ALUoperation
Zero
ALU ALU
result
MemWrite
MemtoReg
Address
Read
data
Data
memory
Write
data
M
u
x
32
MemRead
1998 Morgan Kaufmann Publishers
2
Control
•
Selecting the operations to perform (ALU, read/write, etc.)
•
Controlling the flow of data (multiplexor inputs)
•
Information comes from the 32 bits of the instruction
•
Example:
add $8, $17, $18
•
Instruction Format:
000000
10001
10010
01000
op
rs
rt
rd
00000 100000
shamt
funct
ALU's operation based on instruction type and function code
1998 Morgan Kaufmann Publishers
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Control
•
•
•
e.g., what should the ALU do with this instruction
Example: lw $1, 100($2)
35
2
1
op
rs
rt
16 bit offset
ALU control input
000
001
010
110
111
•
100
AND
OR
add
subtract
set-on-less-than
Why is the code for subtract 110 and not 011?
1998 Morgan Kaufmann Publishers
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ALU Operation
•
•
•
For load and store instruction, use ALU add to compute memory
address.
For R-type instruction, the operation of ALU will be determined by
the funct filed, or the lower 6 bits of the 32-bit instruction.
For branch instructions, use ALU subtraction.
1998 Morgan Kaufmann Publishers
5
Control
•
Must describe hardware to compute 3-bit ALU control input
– given instruction type
00 = lw, sw
ALUOp
01 = beq,
computed from instruction type
10 = arithmetic
– function code for arithmetic
•
An example of multiple level decoding methodology.
1998 Morgan Kaufmann Publishers
6
Setting ALU Control
Instruction ALUOp Operation Funct ALU
LW
00
load
xxxxxx add
SW
00
store
xxxxxx add
Branch Equal 01
beq
xxxxxx sub
R-Type
10
add
100000 add
R-Type
10
subtract 100010 sub
R-Type
10
AND
100100 and
R-Type
10
OR
100101 or
R-Type
10
slt
101010 slt
ALU Ctrl
010
010
110
010
110
000
001
111
1998 Morgan Kaufmann Publishers
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Describing control using a truth table
ALUOp
ALUOp1 ALUOp0
0
0
X
1
1
X
1
X
1
X
1
X
1
X
F5
X
X
X
X
X
X
X
Funct field
F4 F3 F2 F1
X X X X
X X X X
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 0
X 1 0 1
Operation
F0
X
X
0
0
0
1
0
010
110
010
110
000
001
111
1998 Morgan Kaufmann Publishers
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Control Signals
Signal
RegDst
Regwrite
ALUSrc
PCSrc
MemRead
MemWrite
MemtoReg
Deasserted
dest register from rt (20-16)
none
2nd operand from reg output 2
PC<-- PC+4
none
none
put ALU result to reg
Asserted
from rd (15-11)
write to dest register
from 16 bit sign extension
PC<--branch dest
read from memory
write to memory
put memory read data to reg
1998 Morgan Kaufmann Publishers
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Control
0
M
u
x
Add ALU
result
Add
Shift
left 2
RegDst
Branch
4
1
MemRead
Instruction [31 26]
MemtoReg
Control ALUOp
MemWrite
ALUSrc
RegWrite
PC
Instruction [25 21]
Read
register 1
Instruction [20 16]
data 1
Read
register 2
Registers Read
Write
data 2
register
Read
address
Instruction
[31 0]
Instruction
memory
Instruction [15 11]
0
M
u
x
1
Read
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Control and Opcode
• Will use 6 bit opcodes to set the nine
control signals
•Figure 5.27 shows the relationship.
Memto- Reg Mem Mem
Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format
1
0
0
1
0
0
0
1
0
lw
0
1
1
1
1
0
0
0
0
sw
X
1
X
0
0
1
0
0
0
beq
X
0
X
0
0
0
1
0
1
1998 Morgan Kaufmann Publishers
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Control
•
Simple combinational logic (truth tables)
Inputs
Op5
Op4
Op3
ALUOp
Op2
ALU control block
Op1
Op0
ALUOp0
ALUOp1
Outputs
F3
F2
F (5– 0)
Operation2
Operation1
F1
Operation
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
Operation0
F0
R-format
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
1998 Morgan Kaufmann Publishers
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R-type Instruction Execution Phases
•
Fetch instruction from memory, increase PC
0
M
u
x
Add
Add
1
Shift
left 2
RegDst
Branch
4
ALU
result
MemRead
Instruction [31 26]
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite
PC
Instruction [25 21]
Read
register 1
Instruction [20 16]
data 1
Read
register 2
Registers Read
Write
data 2
register
Read
address
Instruction
[31 0]
Instruction
memory
Instruction [15 11]
0
M
u
x
1
Read
Zero
0
M
u
x
1
Write
data
ALU
ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Phase 2
•
Read from two registers
0
M
u
x
Add
1
Zero
ALU ALU
result
Address
Shift
left 2
RegDst
Branch
4
ALU
Add result
MemRead
Instruction [31 26]
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite
Instruction [25 21]
PC
Read
address
Instruction [20 16]
Instruction
[31 0]
Instruction
memory
Read
register 1
Instruction [15 11]
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Phase 3
•
ALU operation
0
M
u
x
Add
Add
1
Shift
left 2
RegDst
Branch
4
ALU
result
MemRead
Instruction [31 26]
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite
Instruction [25 21]
PC
Read
register 1
Read
address
Instruction [20 16]
Instruction
[31 0]
Instruction
memory
Instruction [15 11]
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Phase 4
•
Write result to register.
0
M
u
x
Add
Add
1
Shift
left 2
RegDst
Branch
4
ALU
result
MemRead
Instruction [31 26]
MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite
Instruction [25 21]
PC
Read
address
Instruction [20 16]
Instruction
[31 0]
Instruction
memory
Read
register 1
Instruction [15 11]
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Complete Datapath (Fig. 5-29)
Instruction [25– 0]
26
Shift
left 2
Jump address [31– 0]
28
0
1
M
u
x
M
u
x
ALU
Add result
1
0
Zero
ALU ALU
result
Address
PC+4 [31– 28]
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction [15– 11]
Shift
left 2
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Write
data
Instruction [15– 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5– 0]
1998 Morgan Kaufmann Publishers
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Our Simple Control Structure
•
All of the logic is combinational
•
We wait for everything to settle down, and the right thing to be done
– ALU might not produce right answer right away
– we use write signals along with clock to determine when to write
•
Cycle time determined by length of the longest path
State
element
1
Combinational logic
State
element
2
Clock cycle
1998 Morgan Kaufmann Publishers
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Single Cycle Implementation
•
Calculate cycle time assuming negligible delays except:
– memory (2ns), ALU and adders (2ns), register file access (1ns)
– look at the example in the last part of Sec 5.3
PCSrc
Add
4
Add
RegWrite
Instruction [25 21]
PC
Read
address
Instruction
[31 0]
Instruction
memory
Instruction [20 16]
1
M
u
Instruction [15 11] x
0
RegDst
Instruction [15 0]
Read
register 1
Read
register 2
Read
data 1
Read
Write
data 2
register
Write
Registers
data
16
Sign 32
extend
ALU
result
1
M
u
x
0
Shift
left 2
MemWrite
ALUSrc
1
M
u
x
0
Zero
ALU ALU
result
MemtoReg
Address
Write
data
ALU
control
Read
data
Data
memory
1
M
u
x
0
MemRead
Instruction [5 0]
ALUOp
1998 Morgan Kaufmann Publishers
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Where we are headed
•
Single Cycle Problems:
– what if we had a more complicated instruction like floating point?
– wasteful of area
•
One Solution:
– use a smaller cycle time
– have different instructions take different numbers of cycles
– a multicycle datapath
1998 Morgan Kaufmann Publishers
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High-level Diagram
Instruction
register
PC
Address
Data
A
Register #
Instruction
Memory
or data
Data
Memory
data
register
ALU
Registers
Register #
ALUOut
B
Register #
1998 Morgan Kaufmann Publishers
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Multicycle Approach
•
We will be reusing functional units
– ALU used to compute address and to increment PC
– Memory used for instruction and data
•
Introduce new registers in main functional units
– IR for storing instruction, MDR for storing data read from memory
– A, B registers for storing data read from registers
– ALUOut register for storing ALU results
•
Our control signals will not be determined solely by instruction
•
We will use a finite state machine for control.
1998 Morgan Kaufmann Publishers
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Review: finite state machines
•
Finite state machines:
– a set of states and
– next state function (determined by current state and the input)
– output function (determined by current state and possibly input)
Current state
Next-state
function
Next
state
Clock
Inputs
Output
function
Outputs
– We’ll use a Moore machine (output based only on current state)
1998 Morgan Kaufmann Publishers
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Review: finite state machines
•
Example:
– Output: NSLite, EWLite
– State: NSGreen, EWGreen
– Input: NSCar, EWCar
B. 28: State Diagram
EWcar
NSgreen
EWgreen
NSlite
NScar
______
EWcar
EWlite
______
NScar
1998 Morgan Kaufmann Publishers
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Multicycle Approach
•
Break up the instructions into steps, each step takes a cycle
– balance the amount of work to be done
– restrict each cycle to use only one major functional unit
•
At the end of a cycle
– store values for use in later cycles (easiest thing to do)
– introduce additional internal registers
•
Need more multiplexors since we are sharing functional units (ALU,
memory).
•
Justified since cost of registers and multiplexor is much less than
ALU or memory.
1998 Morgan Kaufmann Publishers
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MIPS Multicycle Datapath
•
PC
handling basic instructions
0
M
u
x
1
Address
Memory
Instruction
[25 21]
Read
register 1
Instruction
[20 16]
Read
Read
register 2 data 1
Registers
Write
Read
register
data 2
MemData
Instruction
[15 0]
Write
data
Instruction
register
Instruction
[15 0]
Memory
data
register
0
M
Instruction u
x
[15 11]
1
A
B
0
M
u
x
1
Sign
extend
32
Zero
ALU
ALU
result
ALUOut
0
4
Write
data
16
0
M
u
x
1
1 M
u
2 x
3
Shift
left 2
1998 Morgan Kaufmann Publishers
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Multicycle Datapath (with control signals)
IorD
PC
0
M
u
x
1
MemRead MemWrite
RegDst
RegWrite
Instruction
[25 21]
Address
Memory
MemData
Write
data
IRWrite
Instruction
register
Instruction
[15 0]
Memory
data
register
0
M
u
x
1
Read
register 1
Read
Read
data 1
register 2
Registers
Write
Read
register
data 2
Instruction
[20 16]
Instruction
[15 0]
ALUSrcA
0
M
Instruction u
x
[15 11]
1
A
B
4
Write
data
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Zero
ALU ALU
result
ALUOut
0
1 M
u
2 x
3
ALU
control
Instruction [5 0]
MemtoReg
ALUSrcB ALUOp
1998 Morgan Kaufmann Publishers
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Multicycle Datapath (complete)
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
Control
MemWrite
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5 0]
0
M
26
Instruction [25 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25 21]
Read
register 1
Instruction
[20 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15 0]
Instruction
register
Instruction
[15 0]
Memory
data
register
0
M
Instruction u
x
[15 11]
1
B
4
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
1 u
x
2
PC [31-28]
0
M
u
x
1
A
28
Jump
address [31-0]
Zero
ALU ALU
result
ALUOut
0
1 M
u
2 x
3
ALU
control
Instruction [5 0]
1998 Morgan Kaufmann Publishers
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Five Execution Steps
•
Instruction Fetch
•
Instruction Decode and Register Fetch
•
Execution, Memory Address Computation, or Branch Completion
•
Memory Access or R-type instruction completion
•
Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
1998 Morgan Kaufmann Publishers
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Step 1: Instruction Fetch
•
•
•
Use PC to get instruction and put it in the Instruction Register.
Increment the PC by 4 and put the result back in the PC.
Can be described succinctly using RTL "Register-Transfer Language"
IR = Memory[PC];
PC = PC + 4;
Can we figure out the values of the control signals?
What is the advantage of updating the PC now?
1998 Morgan Kaufmann Publishers
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Step 2: Instruction Decode and Register Fetch
•
•
•
Read registers rs and rt in case we need them
Compute the branch address in case the instruction is a branch
RTL:
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
•
We aren't setting any control lines based on the instruction type
(we are busy "decoding" it in our control logic)
1998 Morgan Kaufmann Publishers
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Step 3 (instruction dependent)
•
ALU is performing one of three functions, based on instruction type
•
Memory Reference:
ALUOut = A + sign-extend(IR[15-0]);
•
R-type:
ALUOut = A op B;
•
Branch:
if (A==B) PC = ALUOut;
1998 Morgan Kaufmann Publishers
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Step 4 (R-type or memory-access)
•
Loads and stores access memory
MDR = Memory[ALUOut];
or
Memory[ALUOut] = B;
•
R-type instructions finish
Reg[IR[15-11]] = ALUOut;
The write actually takes place at the end of the cycle on the edge
1998 Morgan Kaufmann Publishers
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Write-back step
• Reg[IR[20-16]]= MDR;
1998 Morgan Kaufmann Publishers
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Summary:
Step name
Instruction fetch
Action for R-type
instructions
Instruction
decode/register fetch
Action for memory-reference
Action for
instructions
branches
IR = Memory[PC]
PC = PC + 4
A = Reg [IR[25-21]]
B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address
computation, branch/
jump completion
ALUOut = A op B
ALUOut = A + sign-extend
(IR[15-0])
Memory access or R-type
completion
Reg [IR[15-11]] =
ALUOut
Load: MDR = Memory[ALUOut]
or
Store: Memory [ALUOut] = B
Memory read completion
if (A ==B) then
PC = ALUOut
Action for
jumps
PC = PC [31-28] II
(IR[25-0]<<2)
Load: Reg[IR[20-16]] = MDR
1998 Morgan Kaufmann Publishers
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Simple Questions
•
How many cycles will it take to execute this code?
Label:
•
•
lw $t2, 0($t3)
lw $t3, 4($t3)
beq $t2, $t3, Label
add $t5, $t2, $t3
sw $t5, 8($t3)
...
#assume not
What is going on during the 8th cycle of execution?
In what cycle does the actual addition of $t2 and $t3 takes place?
1998 Morgan Kaufmann Publishers
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Implementing the Control
•
Value of control signals is dependent upon:
– what instruction is being executed
– which step is being performed
•
Use the information we accumulated to specify a finite state machine
– specify the finite state machine graphically, or
– use microprogramming
•
Implementation can be derived from specification
1998 Morgan Kaufmann Publishers
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Graphical Specification of FSM
Instruction decode/
register fetch
Instruction fetch
Start
Memory address
computation
6
(Op = 'LW')
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Branch
completion
8
ALUSrcA =1
ALUSrcB = 00
ALUOp= 10
Memory
access
3
1
Execution
2
Memory
access
5
MemRead
IorD = 1
MemWrite
IorD = 1
Write-back step
RegDst = 0
RegWrite
MemtoReg = 1
How many state bits will we need?
RegDst = 1
RegWrite
MemtoReg = 0
Jump
completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
R-type completion
7
4
•
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
(Op = 'J')
0
PCWrite
PCSource = 10
Finite State Machine for Control
Implementation:
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
Control logic
MemtoReg
PCSource
ALUOp
Outputs
ALUSrcB
ALUSrcA
RegWrite
RegDst
NS3
NS2
NS1
NS0
Instruction register
opcode field
S0
S1
S2
S3
Op0
Op1
Op2
Op3
Op4
Inputs
Op5
•
State register
1998 Morgan Kaufmann Publishers
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PLA Implementation
•
If I picked a horizontal or vertical line could you explain it?
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
PCSource1
PCSource0
ALUOp1
ALUOp0
ALUSrcB1
ALUSrcB0
ALUSrcA
RegWrite
RegDst
NS3
NS2
NS1
NS0
1998 Morgan Kaufmann Publishers
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ROM Implementation
•
•
ROM = "Read Only Memory"
– values of memory locations are fixed ahead of time
A ROM can be used to implement a truth table
– if the address is m-bits, we can address 2m entries in the ROM.
– our outputs are the bits of data that the address points to.
m
n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
m is the "height", and n is the "width"
1998 Morgan Kaufmann Publishers
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ROM Implementation
•
•
How many inputs are there?
6 bits for opcode, 4 bits for state = 10 address lines
(i.e., 210 = 1024 different addresses)
How many outputs are there?
16 datapath-control outputs, 4 state bits = 20 outputs
•
ROM is 210 x 20 = 20K bits
•
Rather wasteful, since for lots of the entries, the outputs are the
same
?i.e., opcode is often ignored
(and a rather unusual size)
1998 Morgan Kaufmann Publishers
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ROM vs PLA
•
Break up the table into two parts
?4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
?10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
?Total: 4.3K bits of ROM
•
PLA is much smaller
?can share product terms
?only need entries that produce an active output
?can take into account don't cares
•
Size is (#inputs  #product-terms) + (#outputs  #product-terms)
For this example = (10x17)+(20x17) = 460 PLA cells
•
PLA cells usually about the size of a ROM cell (slightly bigger)
1998 Morgan Kaufmann Publishers
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Another Implementation Style
Complex instructions: the "next state" is often current state + 1
Control unit
PLA or ROM
Outputs
Input
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
BWrite
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
AddrCtl
1
State
Adder
Address select logic
Op[5– 0]
•
Instruction register
opcode field
1998 Morgan Kaufmann Publishers
44
Details
Op
000000
000010
000100
100011
101011
Dispatch ROM 1
Opcode name
R-format
jmp
beq
lw
sw
Value
0110
1001
1000
0010
0010
Dispatch ROM 2
Opcode name
lw
sw
Op
100011
101011
Value
0011
0101
PLA or ROM
1
State
Adder
3
Mux
2 1
AddrCtl
0
0
Dispatch ROM 2
Dispatch ROM 1
Op
Address select logic
Instruction register
opcode field
State number
0
1
2
3
4
5
6
7
8
9
Address-control action
Use incremented state
Use dispatch ROM 1
Use dispatch ROM 2
Use incremented state
Replace state number by 0
Replace state number by 0
Use incremented state
Replace state number by 0
Replace state number by 0
Replace state number by 0
Value of AddrCtl
3
1
2
3
0
0
3
0
0
0
1998 Morgan Kaufmann Publishers
45
Microprogramming
Control unit
Microcode memory
Outputs
Input
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
BWrite
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
AddrCtl
Datapath
1
Microprogram counter
Adder
Op[5– 0]
Address select logic
Instruction register
opcode field
•
What are the microinstructions?
1998 Morgan Kaufmann Publishers
46
Microprogramming
•
A specification methodology
– appropriate if hundreds of opcodes, modes, cycles, etc.
– signals specified symbolically using microinstructions
Label
Fetch
Mem1
LW2
ALU
control
Add
Add
Add
SRC1
PC
PC
A
Register
control
SRC2
4
Extshft Read
Extend
PCWrite
Memory
control
Read PC ALU
Read ALU
Write MDR
SW2
Rformat1 Func code A
Write ALU
B
Write ALU
BEQ1
JUMP1
•
Subt
A
B
ALUOut-cond
Jump address
Sequencing
Seq
Dispatch 1
Dispatch 2
Seq
Fetch
Fetch
Seq
Fetch
Fetch
Fetch
What would a microassembler do?
1998 Morgan Kaufmann Publishers
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Microinstruction format
Field name
ALU control
SRC1
SRC2
Value
Add
Subt
Func code
PC
A
B
4
Extend
Extshft
Read
ALUOp = 10
ALUSrcA = 0
ALUSrcA = 1
ALUSrcB = 00
ALUSrcB = 01
ALUSrcB = 10
ALUSrcB = 11
Write ALU
RegWrite,
RegDst = 1,
MemtoReg = 0
RegWrite,
RegDst = 0,
MemtoReg = 1
MemRead,
lorD = 0
MemRead,
lorD = 1
MemWrite,
lorD = 1
PCSource = 00
PCWrite
PCSource = 01,
PCWriteCond
PCSource = 10,
PCWrite
AddrCtl = 11
AddrCtl = 00
AddrCtl = 01
AddrCtl = 10
Register
control
Write MDR
Read PC
Memory
Read ALU
Write ALU
ALU
PC write control
ALUOut-cond
jump address
Sequencing
Signals active
ALUOp = 00
ALUOp = 01
Seq
Fetch
Dispatch 1
Dispatch 2
Comment
Cause the ALU to add.
Cause the ALU to subtract; this implements the compare for
branches.
Use the instruction's function code to determine ALU control.
Use the PC as the first ALU input.
Register A is the first ALU input.
Register B is the second ALU input.
Use 4 as the second ALU input.
Use output of the sign extension unit as the second ALU input.
Use the output of the shift-by-two unit as the second ALU input.
Read two registers using the rs and rt fields of the IR as the register
numbers and putting the data into registers A and B.
Write a register using the rd field of the IR as the register number and
the contents of the ALUOut as the data.
Write a register using the rt field of the IR as the register number and
the contents of the MDR as the data.
Read memory using the PC as address; write result into IR (and
the MDR).
Read memory using the ALUOut as address; write result into MDR.
Write memory using the ALUOut as address, contents of B as the
data.
Write the output of the ALU into the PC.
If the Zero output of the ALU is active, write the PC with the contents
of the register ALUOut.
Write the PC with the jump address from the instruction.
Choose the next microinstruction sequentially.
Go to the first microinstruction to begin a new instruction.
Dispatch using the ROM 1.
Dispatch using the ROM 2.
Maximally vs. Minimally Encoded
•
No encoding:
– 1 bit for each datapath operation
– faster, requires more memory (logic)
– used for VAX 780 an astonishing 400K of memory!
•
Lots of encoding:
– send the microinstructions through logic to get control signals
– uses less memory, slower
•
Historical context of CISC:
– Too much logic to put on a single chip with everything else
– Use a ROM (or even RAM) to hold the microcode
– It’s easy to add new instructions
1998 Morgan Kaufmann Publishers
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Microcode: Trade-offs
•
Distinction between specification and implementation is sometimes blurred
•
Specification Advantages:
– Easy to design and write
– Design architecture and microcode in parallel
•
Implementation (off-chip ROM) Advantages
– Easy to change since values are in memory
– Can emulate other architectures
– Can make use of internal registers
•
Implementation Disadvantages, SLOWER now that:
– Control is implemented on same chip as processor
– ROM is no longer faster than RAM
– No need to go back and make changes
1998 Morgan Kaufmann Publishers
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The Big Picture
Initial
representation
Finite state
diagram
Microprogram
Sequencing
control
Explicit next
state function
Microprogramcounter
+ dispatch ROMS
Logic
representation
Logic
equations
Truth
tables
Implementation
technique
Programmable
logic array
Read only
memory
1998 Morgan Kaufmann Publishers
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