Transcript Chapter 2 - 451 Slides

LC3-DC
enaMARM
enaPC
PC
Designing The
LC-3 Control
B
ALU
A
IR
enaALU
enaMDR
ECEn 224
LC3-DC
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BYU
The Von Neumann Model
•
•
•
Fetch an instruction
Execute it
Fetch the next instruction
continue ...
Execute
Fetch
ECEn 224
LC3-DC
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The Fetch Cycle
1.
2.
3.
PC MAR
PC  PC+1,
Mem[MAR]  MDR
MDR  IR
Fetch0
enaPC
ldMAR
selPC = “00”
ldPC
Fetch1
selMDR = ‘1’
ldMDR
Fetch2
ECEn 224
enaMDR
ldIR
LC3-DC
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BYU
A Note on Timing

In all cases:
 Buses are driven and muxes are selected during a
state

Registers and memory inputs are latched on the
rising clock edge at the end of the state
ECEn 224
LC3-DC
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CLK
CS
Fetch 0
Fetch 1
Fetch 2
Fetch0
enaPC
Fetch1
ldMAR
Fetch2
MAR
enaPC
ldMAR
selPC = “00”
ldPC
selMDR = ‘1’
ldMDR
enaMDR
ldIR
MAR actually loads on clock edge
PC contents are driven onto the Bus
ECEn 224
LC3-DC
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CLK
Fetch 0
CS
Fetch0
ldMDR
ldIR
Fetch1
Fetch2
MDR
Fetch 1
Fetch 2
enaPC
ldMAR
selPC = “00”
ldPC
selMDR = ‘1’
ldMDR
enaMDR
ldIR
MDR actually loads on clock edge
Memory is being accessed
and generates its output
ECEn 224
LC3-DC
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CLK
Fetch 0
CS
ldMDR
ldIR
Fetch0
Fetch1
Fetch2
MDR
Fetch 1
Fetch 2
enaPC
ldMAR
selPC = “00”
ldPC
selMDR = ‘1’
ldMDR
enaMDR
ldIR
IR
MDR output is driven onto bus
IR actually loads on clock edge
ECEn 224
LC3-DC
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A Note on PC Incrementing
 The
PC is always incremented during the fetch
process, before the instruction is executed

This means that during instruction execution, PC
points to the next instruction to be executed, not the
instruction being executed
 For
a branch or jump, the PC will get loaded
with a different value during the execution
phase of the instruction
 PC relative addressing is relative to the address
of the next instruction to be executed
ECEn 224
LC3-DC
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The Decode State
from Fetch2
Decode
opCode=0001
opCode=0111
opCode=0010
opCode=0100
ADD0
LD0
STR0
JSR0
…
…
…
…
opCode=1111
…
TRAP0
…
The only state with a conditional branch in the machine…
ECEn 224
LC3-DC
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The Decoder
0000
0001
IR[15:12]
4:16
Decoder
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ECEn 224
BR
ADD
LD
ST
JSR
AND
LDR
STR
RTI
NOT
LDI
STI
JMP
reserved
LEA
TRAP
We could use a decoder
to differentiate between
instructions
LC3-DC
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LEA Instruction
LEA
DR
PCoffset9
c
Send DR field from IR as
address to the register file (a)
PC
Add the contents of the PC to
the sign extended PCoffset9
from the IR to form the
effective address (b)
b
Store the generated address
into the DR (c)
B
A
ALU
How many clock cycles
does all this take?
IR
ECEn 224
a
LC3-DC
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The LEA Instruction
15 14 13 12 11 10
LEA
1110
DR
9
8
7
6
5
4
3
2
1
0
PCoffset9

R[DR]  PC + IR[8:0]

Note that the PC Offset is
always a 2’s complement
(signed) value
LEA0
selEAB1 = ‘0’
selEAB2 = “10”
selMAR = ‘0’
enaMARM
DR = IR[11:9]
regWE
to Fetch0
ECEn 224
LC3-DC
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LDR Instruction
LDR
DR
BaseR
offset6
c
Send BaseR field from IR as
address to the register file (a)
PC
Add the contents of BaseR to
the sign extended offset6 from
the IR to form the destination
memory address for the
STR (b)
Store the generated address
into the MAR (c)
b
B
A
ALU
IR
ECEn 224
a
LC3-DC
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LDR Instruction
LDR
Store the contents of memory to
the MDR (d)
DR
BaseR
index6
PC
Send DR field from IR as address
to the register file (e)
Write the contents of the MDR
into the DR (f)
How many clock cycles
does all this take?
B
A
d
ALU
IR
e
f
ECEn 224
LC3-DC
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The LDR Instruction
15 14 13 12 11 10
LDR



0110
DR
9
8
7
BaseR
6
5
4
3
2
1
0
LDR0
SR1 = IR[8:6]
selEAB1 = ‘1’
selEAB2 = “01”
selMAR = ‘0’
enaMARM
ldMAR
LDR1
selMDR = ‘1’
ldMDR
LDR2
enaMDR
DR = IR[11:9]
regWE
offset6
MAR  R[BaseR]+offset6
MDR  Mem[MAR]
R[DR]  MDR
to Fetch0
ECEn 224
LC3-DC
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LDI Instruction
LDI
DR
PCoffset9
b
d
Add the contents of the PC to
the sign extended PCoffset9
from the IR to form the source
memory address for the
LDI (a)
PC
a
Store the generated address
into the MAR (b)
Load the memory contents
into the MDR (c)
c
B
Load the contents of the MDR
into the MAR (d)
A
ALU
IR
ECEn 224
LC3-DC
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LDI Instruction
LDI
Load the memory contents
into the MDR (e)
DR
PCoffset9
PC
Load the contents of the MDR
into the DR (f)
How many clock cycles
does all this take?
e
B
A
ALU
IR
ECEn 224
LC3-DC
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The LDI Instruction
15 14 13 12 11 10
LDI





1010
DR
9
8
7
6
5
4
3
2
1
LDI0
selEAB1 = ‘0’
selEAB2 = “10”
selMAR = ‘0’
enaMARM
ldMAR
LDI1
selMDR = ‘1’
ldMDR
LDI2
enaMDR
ldMAR
LDI3
selMDR = ‘1’
ldMDR
LDI4
enaMDR
DR = IR[11:9]
regWE
0
PCoffset9
MAR  PC + IR[8:0]
MDR  Mem[MAR]
MAR  MDR
MDR  Mem[MAR]
R[DR]  MDR
to Fetch0
ECEn 224
LC3-DC
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STR Instruction
STR
SR
BaseR
offset6
c
Send BaseR field from IR as
address to the register file (a)
PC
Add the contents of BaseR to
the sign extended offset6 from
the IR to form the destination
memory address for the
STR (b)
Store the generated address
into the MAR (c)
b
B
A
ALU
IR
ECEn 224
a
LC3-DC
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STR Instruction
STR
Send SR field from IR as address
to the register file (d)
SR
BaseR
offset6
f
PC
Store the contents of SR to
the MDR (e)
Perform the memory write (f)
How many clock cycles
does all this take?
PASS
B
A
ALU
IR
ECEn 224
d
LC3-DC
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e
The STR Instruction
15 14 13 12 11 10
STR



0111
SR
9
8
7
BaseR
6
5
4
3
2
1
0
STR0
offset6
MAR  R[BaseR]+offset
MDR  R[SR]
Write memory
STR1
STR2
SR1 = IR[8:6]
selEAB1 = ‘1’
selEAB2 = “01”
selMAR = ‘0’
enaMARM
ldMAR
SR1 = IR[11:9]
aluControl = PASS
enaALU
selMDR = ‘0’
ldMDR
memWE
to Fetch0
ECEn 224
LC3-DC
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STI Instruction
STI
SR
PCoffset9
b
d
Add the contents of the PC to
the sign extended PCoffset9
from the IR to form the source
memory address for the
STI (a)
PC
a
Store the generated address
into the MAR (b)
Load the memory contents
into the MDR (c)
c
B
Load the contents of the MDR
into the MAR (d)
A
ALU
IR
ECEn 224
LC3-DC
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STI Instruction
STI
 Load the contents of the
source register into the MDR (e)
SR
PCoffset9
f
PC
 Load the contents of the MDR
into the DR (f)
How many clock cycles
does all this take?
PASS
B
A
ALU
IR
ECEn 224
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e
The STI Instruction
15 14 13 12 11 10
STI





1011
SR
9
8
7
6
5
4
3
2
1
STI0
selEAB1 = ‘0’
selEAB2 = “10”
selMAR = ‘0’
enaMARM
ldMAR
STI1
selMDR = ‘1’
ldMDR
STI2
enaMDR
ldMAR
STI3
SR1 = IR[11:9]
aluControl = PASS
enaALU
selMDR = ‘0’
ldMDR
STI4
memWE
0
PCoffset9
MAR  PC + IR[8:0]
MDR  M[MAR]
MAR  MDR
MDR  R[SR]
Write memory
to Fetch0
ECEn 224
LC3-DC
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JSRR Instruction
JSRR
0
00
BaseR
000000
a
 Load the contents of the PC
into R7 (a)
‘111’
PC
 Load the contents of the
b
base address register into
the PC (b)
How many clock cycles
does all this take?
B
A
ALU
IR
ECEn 224
LC3-DC
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The JSRR Instruction
15 14 13 12 11 10
JSRR



0100
0
9
00
8
7
BaseR
6
5
4
3
2
1
0
000000
Note: Same opcode as JSR!
(determined by IR bit 11)
R7  PC
PC  R[BaseR]
JSRR0
enaPC
DR = “111”,
regWE
JSRR1
SR1 = IR[8:6]
selEAB1 = ‘1’
selEAB2 = “00”
selPC = “01”
ldPC
to Fetch0
ECEn 224
LC3-DC
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The BR Instruction
BR
15 14 13 12 11 10
9
z
p
0000
n
8
7
6
5
4
3
2
1
0
PCoffset9
Simply check NZP flags with nzp from instruction to
decide whether to ldPC or not
 Method 1: Could bring nzp flags into FSM as inputs
and put comparison into state table… Bad idea



Makes FSM more complicated
Method 2: Do comparison with some external gates
and bring single-bit input into FSM….Good idea
ECEn 224
LC3-DC
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The BR Instruction
BR
15 14 13 12 11 10
9
z
p
0000
n
8
7
6
5
4
3
2
1
0
PCoffset9
BranchTaken = (n • N) + (z • Z) + (p • P)
1 Bit Condition Code Registers
ECEn 224
LC3-DC
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BYU