Transcript Digital Sub

Digital Sub-System
Dorothy Gordon
Cosmic RAy Telescope for the Effects of Radiation
Overview
•
•
•
•
Digital Subsystem Overview/Block Diagram
Developments Since PDR
Design/Implementation Status
Next
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
2
Digital Sub-System Data Flow
Analog
Board
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
Amptek
PH300
Peak Det.
Maxim
MAX145
12 bit A/D
1553 XCVR
Side A
FPGA
RTSX72SU
1553 XCVR
Side B
1 Hz
S/C
RTD
Test Pulse Amplitude
8 bit DAC
Test Pulse Trigger (x2)
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
3
Digital Sub-System Block Diagram
P -LEV EL
0 - 5 V.
8 bit
E CA L-DC
E CA LPW M
PWM to DC
T P-P CK [1: 0]
P CK O UT [1:0]
P CK [1:0]
SRAM
Buffer
Test Pulse I/F
S ngCnt[5: 0]
E CA LPW M
E CA L-PCK [1:0]
LLDT HNP WM
LLDT HK P WM
P DReset [5:0]
A DC-Cnt lDat[5: 0]
1553Dat[ 15:0]
1553Dat[ 15:0]
1553AdrCntl[22:0]
1553AdrCntl[22:0]
Det Tr ig[5: 0]
S ngCnt[5: 0]
CLK 16M
CLK 16M
SCL K
Reset
R ESET
A+
1553 Bus
Protocol
Controller Transceiver
1553_A
AB+
LLDT HI N- DC
~0 - 1.4V.
8 bit
HWReset
CDM-FPGA
LLDT HI NP W M
1553_B
HADRS EL[ 4: 0]
PWM to DC
B-
CLK 1HZ
HADC-CntllDat[ 1: 0]
AE
I/F
LLDT HCK -DC
~0 - 1.4V.
8 bit
LLDT HK P WM
PWM to DC
Power-On
Reset
LLD Threshold
Crater Data Control
P DReset [5:0]
x6
x6
Det SigIn[5: 0]
Peak Detect/Hold
5VN
5VP V CC
A DC-Cnt lDat[5: 0]
DC to DC Conversion
x6
5V_+
EMI
Filter
5VP
5VN
75VN 225VN
28VDC_-
225V_+
Housekeeping
T hickDet BiasEnb
ADC
x2
75V_+
A DC-Cnt lDat[1: 0]
T hinDet BiasEnb
B CLK [1:0]
to Analog Housekeeping
A ET emp[1:0]
28VDC_+
Det Tr ig[5: 0]
Comparator
Analog Signal Processing
Crater Analog Housekeeping
HSK PIN[23:0]
Precondition
Filter/Scale
Analog
Mux
x2
G ND
RT_P
5VP
5VN
T hinDet Bias
Also sent to AE Subystem:
Vref (2.5 V.), Vcc (5V)
and Digital Ground
S/C
1HZ
CLOCK
S/C
I/F
5V
ADC
Vthreshold
T hr Thick
1PP S _-
75VP 225VP
5V_T hr Thin
1PP S _+
Spacecraft Data Interface
OSC
B iasClk[1: 0]
B iasV Enb[1:0]
Det Sig[5:0]
+
Diff.Rcvr
CLK 1HZ
MA DRSE L[4:0]
RTD
t
T hickDet Bias
RT_N
S igG nd
Cosmic RAy Telescope for the Effects of Radiation
28VDC +
RETURN
Developments since PDR
•
•
Requirements – no significant changes
Parts Selection
– DDC BU-63705 for 1553 Bus, Actel SX72, Amptek PH300
– DC-DC Converter Modules (International Rectifier)
•
•
Peak Stretcher (PH300): Performance Verified via Breadboard
Functional Description/Specification
– Details of FPGA operation (Drawing # 32-03010)
•
Schematics
– Board Schematics: released (Drawing # 32-03003)
– Chassis Schematics: released (Drawing # 32-03006)
– High Voltage Power Supply (Drawing #32-03003.01)
• (subcontracted) design complete – prototype in house
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
5
Since PDR (continued)
•
Peer Review (GSFC, May 22, 2006)
– Received/Answered 15 RFAs (for both analog and digital subsystems)
•
•
•
•
•
•
No change to fundamental design of either subsystem
Part type modification (to insure edge-rate compatibility)
Actel Programming Socket exchanged (for “ESD Friendly” replacement)
Actel Static Timing analysis to include asynchronous  clocked path analysis
Signal Integrity and Ground bounce concerns (especially relative to the SX72 FPGA)
Analysis
– Parts Stress Analysis: released (Drawing #32-03010.03)
– Worst Case Analysis: released (Drawing #32-04011.02)
Cosmic RAy Telescope for the Effects of Radiation
Design/Implementation Status
•
FPGA Design
– VHDL Coding Complete (Drawing #32-03003.10)
– Top Level functional simulation complete
– Timing Verified (Static Timer and Dynamic Simulation)
•
Engineering Board (ETU) Layout and Fabrication completed
– Engineering layout is flight part footprint compatible
– High Voltage Supply, implemented on hand-wired breadboard, will be integrated
during the second layout stage
•
ETU Population
– Completion expected by last week of June
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
7
Board Layout
8
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
9
Next
•
•
Design Complete – ready for board level check-out
Next
–
–
–
–
•
Test with GSE
Verify basic functionality/operation
Develop/run marathon diagnostics
Integrate with analog board
Flight Version
– Incorporate any modifications resulting from ETU debug
– Add Bias (High Voltage) Supply
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006
Digital Engineering
10