Transcript Behavioral Modeling of ADC using Verilog-A

Behavioral Modeling of Data Converters
using Verilog-A
George Suárez
Graduate Student
Electrical and Computer Engineering
University of Puerto Rico, Mayaguez
Code 564: Microelectronics and Signal
Processing Branch
NASA Goddard Space Flight Center
Agenda
 Introduction
 Objectives
 Sample and Hold
 Generic data converters models
 Dynamic Element Matching
 Flash ADC
 SAR ADC
 Pipelined ADC
 Second Order ΣΔ Modulator
 Conclusions
 Future Work
 Acknowledgements
 References
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Introduction
 Transistor-level simulation is the most accurate approach.
 Impractical for complex systems, long simulation time!
 Alternate modeling techniques:
Approach
Accuracy
Speed
Flexibility
Device models



Finite-difference equations



Circuit-based macromodels



Time-domain macromodels



Behavioral models



 Can be used in Top-Down design approach.
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Introduction
System Level
(Matlab, C++,
SystemC, AHDLs,
etc…)
Phase
comparator
Loop filter
F(s)
VCO
Functional Level
(SPICE, AHDLs)
A=1
A=1
Behavioral models
fo
--
Vout
Vin
+
V-
V+
Transistor Level
(SPICE)
Layout
Top-Down Design Approach
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Objectives
 Construct behavioral models using the Verilog-A AHDL.
 Simulate some popular ADCs architectures.
 Simulate other common used mixed-signal circuits.
 General modeling for non-idealities.
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Sample and Hold
Φs1
Cs
Ron
Vin
Φs1
1 – exp[-t /(RonCs)]
Thermal noise
Vth ≈ kT/Cs
(Opamp noise neglected)
δ
Vout
Cp
+
CL
Jitter
Φs1
• Finite DC gain A0
2
• Finite GBW
• Cp and CL
Ideal
value
Vout
• Defective settling
• Linear
• Slewing
• Partial Slewing
ωp
H(s) 
ω
2
s 2  p s  ωp
Qp
ω p  2π  GBW
Cs
Cs  C p
|H|
d
x(t+δ) - x(t) ≈ δ
x(t)
dt
εg= 1 - Cs /[ Cs + (Cs + Cp)/A0]
Time
f
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
5
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Jitter Noise
 Non-uniform sampling of the input signal.
δ
ΔV
 Depends on the jitter and the input signal.
 For a sine wave can be approximated by,
x(t+δ) - x(t) ≈ 2πfinδAcos(2πfinnt) ≈ δ
d
dt
x(t)
δ is the sampling uncertainty.
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Jitter Noise
 Assumed to be white noise.
Δt
-Δt
Statistical properties of the jitter
Input signal to the system
0
0
3.01MHz
301 kHz
30.1kHz
-20
100 ps
1 ns
10 ns
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
-60
-80
-100
-60
-80
-120
-100
-140
-120
-160
-180
0
0.5
1
1.5
2
2.5
3
Frequency (Hz)
3.5
4
4.5
5
6
x 10
-140
0
0.5
1
1.5
2
2.5
3
Frequency (Hz)
3.5
4
4.5
5
6
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Thermal Noise
 Fluctuation of carriers due to thermal energy.
 Proportional to the temperature.
 Assumed to be white noise.
0
27 oC
0 oC
-30 oC
-20
-40
27 oC
0 oC
-30 oC
-125.8
-126
-126.2
Magnitude (dB)
Magnitude (dB)
-60
-80
-100
-126.4
-126.6
-126.8
-120
-127
-140
-127.2
-160
1.9995
2
2.0005
2.001
2.0015
2.002
Frequency (Hz)
-180
0
0.5
1
1.5
2
2.5
Frequency (Hz)
3
3.5
2.0025
2.003
2.0035
2.004
6
x 10
4
6
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Sample and Hold model
Thermal
Noise
Ideal S&H
Vin
Filter
Jitter
+
τ = RonCs
Defective
settling
Vout
Vout
Ideal
Nonideal
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Sample and Hold simulation results
PSD for sampled signal of 0 dB, fin = 2.5146MHz N = 8192, BW = 25MHz
0
Ideal
Nonideal
-20
-40
Magnitude (dB)
-60
Increase in noise floor due nonidealities
-80
-100
-120
-140
-160
-180
-200
0
0.5
1
1.5
Frequency (Hz)
2
2.5
7
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Generic DAC
B bits
Mismatch in units!
2B-1
2B-2
1
unit
unit
…
 Mismatch in DAC units.
 INL
 Gain error
 Offset
Thermometer decoder
0.0% DAC mismatch DEM off
0.1% DAC mismatch DEM off
+
Vout
unit
0
unit
Generic DAC model
including mismatch in units
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
0
0.5
1
1.5
Frequency (Hz)
2
2.5
5
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Generic converters model
vadc
N bits
DAC
xa
wa
with
mismatch
α
+
va
offset
Integral Non-linearity
va
+
α
wa
xa
α = gain error
N bits
Ideal
ADC
vadc
offset
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
DEM
 Used to minimize the effect of DAC mismatch.
Spread the error energy
across the spectrum.
Spread the error energy
in certain frequencies.
Magnitude (dB)
Magnitude (dB)
f (Hz)
Magnitude (dB)
Deterministic
Magnitude (dB)
Stochastic
f (Hz)
f (Hz)
 For modeling it is easier to implement a stochastic DEM.
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
DEM model
DAC 0.1% mismatch
0
2B-2
unit
1
0
…
…
Randomize
unit
…
B bits
Thermometer decoder
2B-1
+
0.1% DAC mismatch DEM off
Vout
-20
DEM off
-40
-60
unit
-80
unit
-100
if(DEM_enable) begin
generate i(1,`DAC_UNITS) begin
temp = $dist_uniform(seed, 1, `DAC_UNITS);
if(temp - floor(temp) >= 0.5)
DEM[i] = ceil(temp);
else
DEM[i] = floor(temp);
end
end
// Then select units stored in the array DEM[ ] for conversion
Magnitude (dB)
-120
-140
0
0.5
1.5
1
2.5
2
5
x 10
0
0.1% DAC mismatch DEM on
-20
DEM on
-40
-60
-80
-100
-120
-140
0
0.5
1.5
1
2
2.5
5
Frequency (Hz)
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Flash ADC
+Vref
R
+
-
R
Cadence provides a well accepted
OPAMP behavioral model !
…
…
R
Encoder
+
…
…
• Finite DC gain
• Finite GBW
• Input resistance
• Output resistance
• Max current
• Offset voltage
• Slew Rate
R
N bits
R
+
-
R
+
-Vref
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Flash ADC simulation results
PSD plot for 8-bit Flash ADC with 0 dB input signal fin of 3.01MHz, Samples = 4096, BW = 5MHz
0
Ideal
Nonideal
-10
-20
-30
Magnitude (dB)
-40
SNDR (dB)
49.264
44.408
SNR (dB)
49.323
44.481
THD (dB)
-67.954
-62.193
SFDR (dB)
60.778
47.261
ENOB
7.9
7.1
-50
-60
-70
-80
-90
-100
-110
0
0.5
1
1.5
Ideal SNR
6.02N+1.76 = 49.92 dB ≈ 50dB
2
2.5
Frequency (Hz)
3
3.5
4
4.5
5
6
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
SAR ADC
Start
CLK
EOC
CONV
Timing
control
SAH
Vin
Sample
& hold
Successive
Approximation
Register
(SAR)
+
-
Anti-aliased signal
N bits
DAC
VDAC
N bits
Register
Vref
¾ Vref
CLK
½ Vref
Start
Vin
¼ Vref
SAH
time
bit 3=0
(MSB)
bit 2=1 bit 1=0 bit 0=1
(LSB)
CONV
Conversion time
EOC
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
SAR 8-bit ADC simulation results
Ideal PSD plot for 8-bit SAR ADC with 0 dB input signal
Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz
20
0
-20
SNDR (dB)
49.823
SNR (dB)
49.949
THD (dB)
-65.263
SFDR (dB)
67.353
ENOB
8.0
Magnitude (dB)
-40
-60
-80
-100
-120
-140
0
0.5
Ideal SNR
6.02N+1.76 = 49.92 dB ≈ 50dB
1
1.5
Frequency (Hz)
2
2.5
5
x 10
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
SAR 8-bit ADC simulation results
PSD plot for 8-bit SAR ADC with 0 dB input signal
Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz
0
0.1% DAC mismatch DEM on
0.1% DAC mismatch DEM off
-20
Increase in harmonics due
mismatch in DAC units
Magnitude (dB)
-40
SNDR (dB)
43.42
45.95
SNR (dB)
47.43
45.99
THD (dB)
-45.61
-66.38
SFDR (dB)
47.74
48.78
ENOB
6.9
7.3
-60
-80
-100
-120
-140
0
0.5
Ideal SNR
6.02N+1.76 = 49.92 dB ≈ 50dB
1
1.5
Frequency (Hz)
2
2.5
5
x 10
19
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Pipeline ADC 8-bit
dout
8 bits
Digital correction
2 bit
2 bit
2 bit
2 bits
2 bit
2 bits
Φ1
Registers
Φ2
2 bit
Vin
Anti-aliased
signal
Sample
& hold
Φ1
2 bit
Stage1
Stage2
Φ2
Φ1
Stage6
Φ1
1.5 bit
ADC
Φ2
Φ1
Φ2
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
1.5-bit Pipelined Stage
MDAC
+
+
Vin
2 bits
1.5 bit
ADC
1.5 bit
DAC
+
1.5 bit
GenericADC
Residue
Residue amplifier
MDAC
Thermal
Noise
Vin
-
2
VADC
1.5bit MDAC
Including
mismatch
Defective
settling
Vres
2-bits
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Pipelined 8-bit ADC simulation results
PSD plot for 8-bit Pipelined ADC with 0 dB input signal
Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz
0
Non-ideal
Ideal
-20
Magnitude (dB)
-40
SNDR (dB)
44.922
48.577
SNR (dB)
49.573
49.238
THD (dB)
-49.923
-57.082
SFDR (dB)
54.427
61.778
ENOB
7.2
7.8
-60
-80
-100
-120
-140
0
0.5
1
1.5
Ideal SNR
6.02N+1.76 = 49.92 dB ≈ 50dB
2
2.5
Frequency (Hz)
3
3.5
4
4.5
5
6
x 10
22
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Second-Order ΣΔΜ Model
• Single pole OTA model
• Defective settling
Ideal
value
settling error
Va
OTA + switches for both
phases Φ1 and Φ2
Integration Φ2
Thermal
Noise
Vin
Jitter
+
Thermal
Noise
SC intg
g11
g21
g12
mismatch
Time
SC intg
DAC
∫
+
Sampling Φ1
g22
∫
5-level 3-bits
Flash ADC
3-bits
DAC
4-bits
4-bits
Decoder
ILA
4-bits
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
ΣΔΜ Simulation Results GSM mode
*Second order sigma-delta modulator with -6 dB input signal
Input frequency of 30kHz, OSR = 65, N = 65536, BW = 200kHz (GSM mode)
VHDL-AMS 74.0164 dB
Actual data 74.5000 dB
0.65% error
*This work has been accepted as a lecture presentation at the IEEE MWCAS 2005 conference, August 7-10 Cincinnati, Ohio.
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Conclusions
 Behavioral modeling is a viable solution for the modeling of
mixed-signal circuits.
 Verilog-A AHDL supports behavioral modeling and; provides
modularity and flexibility.
 Accurate behavioral models are achieved via validation.
 Behavioral modeling can be used as part of a Top-Down design
approach.
 Effective circuits modeling requires deep analysis including
noise sources.
25
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Future Work
 Include more ADCs architectures.
 Add specific DAC architectures.
 Explore current based techniques.
 Validate some of the models.
26
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Acknowledgments
 Dr. Umesh Patel
 Dr. Manuel Jimenez
 Bob Kasa
 Wesley Powell
 Ellen Kozireski
 George Schoppet
 Alex Dea
 Damon Bradley
 Porfi Beltrán
 Irving Linares
 Amandeep Kaur
 Aaron Dixon
 George Winkert
27
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
References
 M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA CONVERTERS FOR
COMMUNICATIONS”, Kluwer Academic Publishers, 2002.
 A. Rodriguez-Vazquez, F. Medeiro and E. Janssens. “CMOS Telecom Data
Converters”. Kluwer Academic Publishers, 2003.
 F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez. “TOP-DOWN ESIGN OF
HIGH-PERFORMANCE SIGMA-DELTA MODULATORS”, Kluwer Academic
Publishers, 1999.
 D. Fitzpatrick and I. Miller. “ANALOG BEHAVIORAL MODELING WITH THE
VERILOG-A LANGUAGE”, Kluwer Academic Publishers, 1998.
 B. Razavi. “Principles of Data Conversion System Design”. IEEE Press, 1995.
 T. M. Hancock. S. M. Pernia and A. C. Zeeb. “A Digitally Corrected 1.5-Bit/Stage
Low Power 80Ms/s 10-Bit Pipelined ADC”. University of Michigan EECS 598-02,
December 2002.
 M. Anderson, K. Norling and J. Yuan. “On the Effects of Static Errors in a Pipelined
A/D Converter”. SSoCC 2003.
 R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K.
Einwich, C. Clauss, P Schwarz and G. Noessing. “From System Specifications To
Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal
Applications. Proc. of the 2002 Design, Automation and Test in Europe, 2002.
 N. Mohan. “Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A“,
www.techonline.com .
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
References
 J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA
CONVERTERS” PhD Dissertation, University of Nevada Las Vegas , May 2000.
 K. Kundert. “Top-Down Design of Mixed-Signal Circuits”. Cadence Design Systems,
San Jose, California, 2000.
 K. W. Current, J. F. Parker, and W. J. Hardaker, “On Behavioral Modeling of Analog
and Mixed-Signal Circuits”. IEEE Conference Record of the Twenty-Eighth Asilomar
on Signals, Systems and Computers, vol. 1, pp264 – 268, 1994
 F. O. Fernandez “Behavioral Modeling of ΣΔ Modulators”. Master’s Thesis University
of Puerto Rico. Mayaguez, Puerto Rico 2003.
 T. Kugelstadt. “The operation of the SAR-ADC based on charge redistribution” TI
Analog Applications Journal, Texas Instruments, 2000.
 J. Compiet, R de Jong, P, Wambacq, G, Vandersteen, S. Donnay, M. Engels and I.
Bolsens. “HIGH-LEVEL MODELING OF A HIGH-SPEED FLASH A/D CONVERTER
FOR MIXED-SIGNAL SIMULATIONS OF DIGITAL TELECOMMUNICATION
FRONT-ENDS”. IEEE SSMSD, pp. 135 – 140, 2000.
 B. Brannon. “Aperture Uncertainty and ADC System Performance”. Analog Devices
APPLICATION NOTE AN-501.
 “Understanding SAR ADCs”. Maxim-IC Application Note 387: Mar 01, 2001.
 “Understanding Pipelined ADCs”. Maxim-IC Application Note 383: Mar 01, 2001.
 “Understanding Flash ADCs”. Maxim-IC Application Note 810: Oct 02, 2001
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
#include <stdio.h>
int main ()
{
char str [100];
printf (“Questions?“);
scanf ("%s",str);
return 0;
}
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Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing
Acronyms
ADC – Analog-to-digital converter
AHDL – Analog Hardware Description Language
DAC – Digital-to-analog converter
DEM – Dynamic Element Matching
ENOB – Effective number of bits.
FS – Full scale voltage
GBW – Gain bandwidth
ILA – Individual Level Averaging
INL – Integral non-linearity
MDAC – Multiplying DAC
SAR – Successive Approximation Register
SFDR - Spurious Free Dynamic Range
SNDR – Signal-to-noise plus distortion ratio
SNR – Signal-to-noise ratio
THD – Total Harmonic Distortion
ΣΔΜ – Sigma-Delta Modulator
31
Behavioral Modeling of ADCs using Verilog-A
by George Suárez
NASA Goddard Space Flight Center
Code 564 Microelectronics and Signal Processing