Transcript I/O Power Delivery - download.intel.nl

I/O Power Delivery
Background Reading
Chap 12.12, 13.7
Hall, Hall & McCall Chap. 6.2
12/4/2002
2
Power Delivery Introduction
 In general power delivery analysis at the board level


is very difficult.
Determining the voltage at any point in time on an
entire board is akin to predicting the weather.
There are fairly good estimation methods for
determining the effects of chip load, power planes,
and capacitors.
Determining effects of signaling on the board power
becomes very complex.
 Chip manufacturers have reasonably good methods
for determining the power delivery to the silicon
from the board.
This is only for a single chip.
We will call this the traditional analysis
The second and more interesting topic is the effect of I/O
switching on chip power and vice versa.
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Topics
 We will introduce the traditional methods first, then





spend most of the time on I/O power delivery.
The method we will talk about in the I/O power
delivery section will be simple but illustrates some
profound effects.
Power delivery “noise” can create EMI which we will
not cover.
Robust treatment of power delivery is a great topic
for research.
One point to consider is that ideal power delivery is
an impedance of 0 ohms between generation and
utilization.
Now consider that measuring impedances near 0
ohms has a number of challenges. Again another
good topic for research.
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Traditional Power Delivery Analysis
 The traditional method is basically evaluating the

step response of the PDN (power delivery network)
A simple outline of the simulation steps is as follows.
Create system model
May be reduced to simple RLC ladder.
More complete analysis may use bed-spring models or S
parameters.
The die is divided into di/dt regions.
In simulation place di/dt loads at the die regions with
voltage controlled resistors driven by scaled current steps.
Then evaluate waveform regions of the largest specified
step response
 This analysis is usually focused on the charge cycle.
The high di/dt creates a demand. We need to measure how
well the rest of the PDN works to stabilize the voltage.
This is done by evaluating each droop and then trying to
associate it with each PDN design domain.
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5
Example of Simple Traditional Method
Regulator
We just look for droops and
spike on the delivered
power rail
Board
High current
di/dt ~
amps/microsecond
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Resonance
 Traditional analysis does not comprehend
feedback and interaction between data
switching and PDN resonance.
 The di/dt are aggregate responses from
silicon blocks of relatively uncorrelated
switching of millions very small transistors.
 I/O buffers are large, have high power
demand, and are synchronized in time.
 We will start the story with the I/O
signaling
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Hypothetical Signaling
7
J
X
I/O Signal at
receiver pin
X
I/O Signal at
receiver pad
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X
Received I/O
signal
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Ideal I/O Signal
8
Received signal
0.8
volts
0.6
Threshold
Levels
0.4
0.2
0
0
2
4
6
8
10
ns
12
14
16
18
20
I/O signal
Vih
Vil
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Ideal Receiver Output
9
Received signal
Received
I/O signal
4
volts
3
2
1
0
0
2
4
6
8
IO signal @ pad
10
ns
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14
16
18
20
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Power Story
10
What
happens if
power does
this once in
a while?
Vcc
Rail
X
Vss
Rail
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Power Noise Can Cause Missed Data
Received signal
Received I/O signal
volts
0.7v
0.8
3.3v
0.6
0.4
0.2
ov
0
ov
0
2
4
6
IO signal @ pad
I/O signal
Vih
Vil
Results
8
10
ns
12
14
16
18
20
in Transient Failure
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Assignment 3 extra credit: Show Power
Noise Can Cause Signal Distortion
Vdie
 Use circuit at


the right
Find the value
of Cdie that
limits the
ripple to 10%
(peak to peak)
Plot the
impedance vs.
frequency
looking out of
node Vdie for
the solution
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I/O Signal – Power Dependence
13
Can this
cause
data
this?
Vcc
Yes!
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Circuit Modeling
 History:
I/O power for Intel® Pentium®
processor GTL+
Just used L*di/dt and capacitive
droop (traditional method)
 New signaling presents additional
power issues
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Pentium® 4 Buffers – On die
termination
Die
Die
Need to
keep
power
rail stiff
Board
Board
Required for
transmission line
signal integrity
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On Die Termination – Drawbacks
and Solution
 Watts!
 Very high instantaneous
current demand
 Package transmission lines
cause very high speed return
currents
 Solution: Add on-die I/O
power capacitance.
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Die
Board
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Estimating I/O Power Delivery Impact
 Concept building
 Example
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Define Power Domains
18
Mid Tier Caps
VRM
Die Caps
Package
Bulk Caps
Package Caps
Do not always exist!
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Simple Concept : Keep buckets filled
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20
Keep this flow in mind
Increasing
frequency
content
VRM
It’s tempting to view this circuit
analysis backward – more later
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Buckets (capacitors) are filled at
different rates, by different paths
 Fill rates are different
Lower frequencies apply as path gets
closer to VRM
 Transmission line return is a high
speed path
 High speed path and low speed path
may be different.
Low frequencies disperse over larger
areas
 Conclusion: Can analyze return path
and I/O power delivery (PD)
independently
There are caveats
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Overall Response of PD is Simple:
22
 Method: cascade resonant tank circuits
 A tank circuit is just an LC network
 Insight from PD with tank analysis
E.g. what really matters
 Challenge: Reduce circuit for simple analysis
… 90% solution
 “End game” – use more sophisticated tools …
better accuracy
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VRM
Die to Package Stage
Inductance
between die
and package
Die
Cap
Note: Inductance includes series resistance (ESR)
capacitance includes series inductance (ESL), resistance (ESR)
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VRM
Package to Mid-Tier Stage
Inductance
between package
and mid-tier cap
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Package
Cap
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VRM
Mid-Tier to Bulk Stage
Inductance
between mid-tier
and bulk cap
Mid Tier
Cap
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VRM
Bulk to VRM Stage
Inductance
between bulk cap
to VRM (including
VRM L)
Bulk
Cap
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Example
27
 Concept of squares for estimation
 Develop some real values
 Determine sensitivities
 Draw some conclusions
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Estimating L from a “square”
Power
Pins
28
Power Plane
Separation
Power
Cap Pads
Ground Plane
Let separation =20 mils
= 1.75 sq
¼ sq
(4 sq
in ||)
½ sq
(2 sq
in ||)
1 sq
Draw Guide
lines
L=32 pH/mil separation /sq
L= 32 ph *20*1.75
L= 1.12 nH
Estimate an average cross-sectional
power delivery line
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Scaling
 In this example we will analyze all the
buffers on a bus.
 We will use the parameter “Ndriver” to
indicate how many buffers are on a
given bus (all on one power rail)
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Example Values – “Die2Pkg”
Rough Scaled Guess
L via
pH
L= 32
mil_separation.sq N vias
C = Cdie .N drivers
 The may be some number of vias (“Nvias”) that connect the chip




power to the package power.
Lvia is the inductance we will use for each via.
All the vias are in parallel so the equivalent inductance of the
network is just Lvia divided by Nvia
Ndrivers is the number I/O buffers.
All the Cdie capacitors are in parallel and thus the equivalent
capacitance is just the sum of all the die capacitors.
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Example Values – “Die2Pkg”
 32 pH 120mm 1sq  .5 nH  5
 milsq


4 
40

40 vias @ 0.5nH/Via +
pH 1 *120
32
mm Plane separation= 50 pH
. * sq
mil sq 4
88 drivers @ 100 pF/driver = 8.8 nF
Better Guess –> 3 D Field
Solver
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Model of Capacitor and Terminology
ESR: Equivalent Series Resistance
ESL: Equivalent Series Inductance
C: Capacitance
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Example Values – “Pkg2Mid”
Rough Guess Scaling Equations
L via
pH
L= 32
mil_separation.sq N vias
C= C cap .N Cap
 The will likely be some number of vias (“Nvias”) that connect the




package power to the board power.
Lvia is the inductance we will use for each via.
All the via are in parallel so the equivalent inductance of the
network is just Lvia divided by Nvia
Ncap is the number of mid tier caps.
All the package capacitors are in parallel and thus the equivalent
capacitance is just the sum of all the package capacitors.
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“Pkg2Mid” parameter assignment
• 15 mil separation, ½ sq
• Two 2.2 mF IDC package caps
– ESL = 80 pH
– ESR = 100 mW
• 20 Vias at 0.7 nH/via
L = 275 pH
Real capacitor
C = 4.4 mF
ESL = 40 pH
ESR= 50 mW
Better Guess –> 3 D Field Solver
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Example – “Mid2Bulk”
Rough Guess
pH
mil_separation.sq
C= C cap .N Cap
VRM
L= 32
• 15 mil separation, 3 sq
L = 1.4 nH
• Fifteen 0.1 mF caps
C = 1.5 mF
ESL = 33 pH
ESR = 40 mW
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– ESL= 500 pH
– ESR= 0.6 W
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Example - “Bulk2VRM”
VRM
Rough Guess
L = 1 nH
pH
L= 32
.
mil_separationsq
C= C cap .N Cap
• 15 mil separation, 2 sq
• Two 500 mF caps
C 1000 mF
ESL = 250 pH
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– ESL=500 pH
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Example Used for Analysis
die2pkg
pkg2mid
L6
50ph
0/1V
Vddp
mid2bulk
L5
275p
L3
1.4n
7n
+
200 MHz
-
.05
ESR
.0003
DieR
8.8nf
Cdie
A
40ph
ESL
.04
ESR
33pH
ESL
4.4uf
Assignment 4 – Use
PSpice to plot impedance
vs. frequency (1 KHz –
1GHz) looking from A and
then B
Cpkg
1.5uf
C board
0.15
ESR
B
.250nh
ESL
1000uF
C Bulk
Actually, any spice simulator
can do this
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Estimate frequency response in MathCAD
p ar( a  b )  
ZC( c  f)  
a b
a b
1
2  f c i
ZL( l  f)   i  2  f l
9
nH 10
 12
h enry p H   1 0
h enry
i max  5 00 0 i   1 .. i max
fmi n   .1MH z
f   fmi n 
i
fmax   1 00 0MH z
( fmax  fmi n)
i max  1
 ( i  1)
Zpk g( f)   Rp k  ZL( Lp k f)  ZC( Cp k f)
 Define functions
 Define constants and frequency array
Lmd f)  ZC( Cmd  f)
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39
MathCad Functions
p ar( a  b )  
ZC( c  f)  
a b
ab
1
2  f c i
ZL( l f)   i  2  f l
L( Lmd f)  ZC( Cmd  f)
9
 12
n H  Parallel
1 0 h enry
H   1 0 h enry
Circuitp function
i max  5 00 0 i   1 .. i max
Capacitor function
fmi n   .1MH z
fmax   1 00 0MH z
Inductor
function
( fmax
 fmi n)
f   fmi n 
i
i max  1
 ( i  1)
Zpk g( f)   Rp k  ZL( Lp k f)  ZC( Cp k f)
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Define Components
p ar(
Rb u   .1 5W
Cb u   1 00 0mF Lb u   .2 50n H
Rmd   .1 0W
Cmd   1 .5mF
Lmd   3 3p H
Rp k   .0 5W
Cp k   4 .4mF
Lp k  4 0p H
Lv rm  6n H
Lv 2b k  1n H
Lb k2 md  1 .4n H
Cd ie  8 .8n F
Rd ie  .0 1W
ZC( c
Zdi e( f)   ZC( Cd ie f)
ZL( l
Lmd 2p k  2 75p
 H Lp k2 di e  5 0p H
Parameters for PDN circuit
 {}bu corresponds to the bulk capacitor
 {}md corresponds to the mid tier capacitor
 {}pk corresponds to the package capacitor
 {}die corresponds to the I/O die power decoupling
 {}2{} corresponds to inductance between two respective regions
 Zdie(f) convert the capacitor to a usable impedance verse
frequency.
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Building a circuit with threading
Zbu lk( f)  Rb u  ZL( Lb u f)  ZC( Cb u f)
Zmd ( f)  Rmd  ZL( Lmd f)  ZC( Cmd  f)
Zpk g( f)  Rp k  ZL( Lp k f)  ZC( Cp k f)
Z1( f)  p ar Zbu lk( f)  ZL( Lv rm f)  ZL( Lv 2b kf
 )  Z2( f)  p ar Z1( f)  ZL( Lb k2 mdf
 )  Zmd ( f) 
Z3( f)  p ar Z2( f)  ZL( Lmd 2p kf
 )  Zpk g( f) 
Zin( f)  p ar Z3( f)  ZL( Lp k2 dief
 )  Rd ie Zdie( f) 
 Start at the bulk cap and thread the circuit
inward to the die
 Zbulk is the impedance associated with the
bulk resistance, impedance of the
capacitance, and the impedance of the
inductance
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Examine Results of Zin vs. Frequency
Ohms
0.224
Zin fi
1
0.1
0.012 0.01
0.1
0.1
1
10
fi
100
1 .10
3
3
110
MHz
MHz
Notice the peaks and the values of
impedance
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Power Impedance Looking Outward From
Die to VRM from simulation
Ohms
1
Note: DV = Z *Di
186 MHz
Resonance
0.1
0.01
0.001
0.1
1
10
MHz
100
1000
Review: Zero ohms is ideal!
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Look in Time Domain: 500 MHZ
Power Rail
Ohms
Digital Data
1
0.1
0.01
0.001
0.1
1
10
MHz
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100
1000
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Look in Time Domain: 186 MHZ
Power Rail
Ohms
Digital Data
1
0.1
0.01
0.001
0.1
1
10
MHz
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100
1000
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VRM
Let’s see what
happens when package caps are
removed.
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Now Look What Happens
in Frequency Domain
1
Ohms
Without package cap
0.1
With Package cap
0.01 Impedance at 200MHz is lower. If
the Data rate is 200MHz the power
noise may actually be reduced!
0.001
0.1
1
10
100
1000
MHz
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Lets vary 200 MHz in the time
domain
Digital Data
Ohms
Power Rail
1
0.1
0.01
0.001
0.1
1
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10
MHz
100
1000
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Now Look What Happens at 100 MHZ
Digital Data
Ohms
Power Rail
1
0.1
0.01
0.001
0.1
1
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10
MHz
100
1000
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50
What is important?
 Critical Resonance
 On-die cap and inductance to next cap
Plus ESL of that cap
Die
Cap
Not the resonance (remember
“backwards” from earlier?)
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Other Factor – Return Path
 Non TEM or …
 Anywhere a signal return is not a
transmission line … e.g. boundaries
Pins
Anti-vias
 Effect is to increase inductance to either
power or ground circuit.
 Need 3-D tools to evaluate
Mutual coupling is important
Plane shape may have its own resonance
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We need to add an extra scaled load to simulate
data with I/O power delivery. If not, we need to
scale the entire power driver for the number of
buffers in the simulation. On Die Power
Delivery
package
Mid Cap
Pkg Cap
Bulk Cap
VRM
Package
Return
path
Scale to total
drivers – N
drivers
I/O Power Delivery
N Coupled
Tlines on
package
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Key Takeaways
53
 I/O PD is part of signaling solution space
 On die decoupling may introduce PD
resonance issues
 Follow I/O PD guidelines if you don’t have
detail chip data
 Modeling
Use info from frequency domain to seed time
domain simulation
Still need to do L*di/dt and droop work too
2 Level approach to I/O power model
First: estimates based on L per square.
Next: refine w/ 3-D modeling
Return path modeling
Evaluate at boundaries
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Summary
54
 Power variations can be data sensitive
 New technology many require new PD analysis
 I/O power resonance is “die outward “not
“die inward”.
 Frequency analysis is important for I/O PD
 PD can be merged into I/O simulations
 Higher frequencies will require us to explore
more higher order effects.
 Take I/O decoupling guideline seriously
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55
Assignment 5: MathCad Power Calculator
Handi-Dandi Powe r De live ry Spectrum Analyze r
Ri chard Mell i tz - I ntel
® - 9/ 13/99
p ar( a  b )  
Rb u   .1 5W
Cb u   1 00 0mF Lb u   .2 50n H
Rmd   .1 0W
Cmd   1 .5mF
Lmd   3 3p H
Rp k   .0 5W
Cp k   4 .4mF
Lp k  4 0p H
Lv rm  6n H
Lv 2b k  1n H
Lb k2 md  1 .4n H
ZC( c  f)  
a b
ab
1
2  f c i
ZL( l f)   i  2  f l
9
nH 10
 12
h enry p H   1 0
i max  5 00 0 i   1 .. i max
fmi n   .1MH z
f   fmi n 
Zbu lk( f)   Rb u  ZL( Lb u f)  ZC( Cb u f)
Zmd ( f)   Rmd  ZL( Lmd f)  ZC( Cmd  f)
fmax   1 00 0M H z
( fmax  fmi n)
i
Lmd 2p k  2 75p
 H Lp k2 di e  5 0p H
h enry
i max  1
 ( i  1)
Zpk g( f)   Rp k  ZL( Lp k f)  ZC( Cp k f)
Cd ie  8 .8n F
Z1( f)   p ar Zbu lk( f)  ZL( Lv rm f)  ZL( Lv 2b kf
 )
Z2( f)   p ar Z1( f)  ZL( Lb k2 mdf
 )  Zmd ( f) 
Zdi e( f)   ZC( Cd ie f)
Z3( f)   p ar Z2( f)  ZL( Lmd 2p kf
 )  Zpk g( f) 
Zin( f)   p ar Z3( f)  ZL( Lp k2 di ef)  Zdi e( f) 
1
0.1
Ohms
Z
0.01
1 .10
3
0.1
1
10
MHz
100
1 .10
3
Embedded MathCad OLE
I/O Power Delivery
Create plot
with all the
caps and
inductors
doubled
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