Transcript Delft, january 1999

Specification and design of a complex system:
The ASML waferstepper
Gerrit Muller
7-1-1999
Delft
Seminar Productieautomatisering 2000+
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The Market
1997
semiconductor sales
by end-use rmarket
GDP
33.4 T$
2002
39.4 T$
3%
non PC
computing
PC’s
32%
consumer
electronics
16%
IC’s
communications
17%
memory
18%
other
applications
electronic
sales
17%
other
semiconductors
3%
902.4G$ 1284.2G$
17%
semiconductor
151.7G$
sales
26%
330.6G$
15%
Equipment
sales
equipment
steppers
ASML
sales 1997:
net income:
1.8 Gfl
0.3 Gfl
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Steppers
22.3G$
13%
42.8G$
16%
17%
3.6G$
7.3G$
source: Dataquest, ING Barings research
www.asml.com
Gerrit Muller
What is a waferstepper?
Lightsource
Mask (Reticle)
Lens
Die
Wafer
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Step & Scan technology
reticle
Scanning
fieldsize
Slit
Lens
Lens
wafer
250 mm/s
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Stepping
fieldsize
Main specifications
Imaging
Overlay
linewidth: 180 nm (1999)
AA (single machine) 40 nm
BC (matched)
60 nm
critical dimension control
For comparison:
Wafer diameter 200 mm
Die size ca.: 20*20 mm2
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Productivity
96 Wafers per hour
Products
Non opto
300 mm,
high throughput
Steppers
5500
i-line
Scanners
248nm
248nm
i-line
193nm
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2 kHz laser
Athena/TIS
Quadrupole
Product roadmap
T1100 193 nm scanner
Atlas 300 mm body
S400 I-line scanner
S700 DUV scanner
T400 I-line scanner
T700 DUV scanner
/900 193 nm scanner
5500 scanner body
/400 i-line scanner
/500 DUV scanner
/300C DUV stepper
/700 DUV scanner
/300D
5500 stepper body
/250C i-line stepper
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Mechanical Design
• dynamic performance
• stage technology
• servo technology
• cooperation with Philips CFT, NatLab
• design rule: 10 nm-> 1 nm -> subnanometer
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Example dynamic performance
many
cables
6 degrees of freedom:
• x, y, Rz
• z, Rx, Ry
• v = 250 mm/s
• a = 10 m/s2
• control frequency: 4 kHz (250 sec)
• position measerument by interferometers
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Optics design
• Projection design
• Illumination
• Light source (lasers)
• Intensity, abberations, distortion, stray light, uniformity
• cooperation with Zeiss, Cymer
• 365 nm -> 248 nm -> 193 nm (-> 157 nm?)
• extensive modelling and simulation
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Example projection design
ca 12 lens elements
• temperature and pressure controlled
• anti reflection coatings
• 193 nm CaF
1 m.
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Control architecture
• Functions implemented in software:
• Calibration, Preparation, Expose, Batch control
• Electronics infrastructure
• Integration
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Modular subsystems
illuminator
reticle
handling
light source
reticle stage
measurement
lens
UI
console
wafer
handling
wafer stage
base frame
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contamination
and
temperature
control
electronics
cabinets
System engineering
imaging
overlay
productivity
mechanics
optics
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control
measurement
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contamination &
temperature
Overlay budget
Reticle
15 nm
Process
Overlay
80 nm
Matched
Machine
60 nm
Process
dependency
sensor
5 nm
Lens
Matching
25 nm
Off axis
Sensor
repro
3 nm
Stage Al.
pos. meas.
accuracy
4 nm
Blue align
sensor
repro
3 nm
System
adjustment
accuracy
2 nm
Single
Machine
30 nm
Matching
Accuracy
5 nm
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Global
alignment
accuracy
6 nm
Off axis
pos meas
accuracy
4 nm
Stage
overlay
12 nm
Position
accuracy
7 nm
Stage grid
accuracy
5 nm
alignment
repro
5 nm
Metrology
stability
6 nm
Gerrit Muller
tracking
error X, Y
2.5 nm
tracking
error phi
75 nrad
Frame
stability
2.5 nm
Interferometer
stability
1 nm
tracking
error WS
2 nm
tracking
error RS
1 nm
Development phases
0
1
feasibility
definition
2
system design subsystem spec
business
impact
prs
sps
sds
tps
alfa test TAR
beta test TAR
plan
cost, effort,time
integration
plan
3
subsystem
design
engineering
eps
eds
tps
prototype
tpd
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
4
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integration
verification
field monitoring
SPS contents checklist
0
1
feasibility
definition
2
system design
3
subsystem spec
overview
doc tree, structure
product lifecycle
option structure
draft
performance requirements
• imaging
• overlay
• throughput
functional requirements draft
• functional model (extern) draft
operations requirements draft
• serviceability
• manufacturability
option structure
functional requirements
• functional model (extern)
• factory integration
• user interface
operations requirements
• serviceability
• manufacturability
environment requirements
• wafer, reticles
• power, gases, water, etc.
• weight size
•transport
machine requirements
• design constraints, f.i. robustness
• safety
• reliability
• COG, COO
• interoperability
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subsystem
design
engineering
SDS contents checklist
0
feasibility
1
2
definition
doc tree, structure draft
system design
3
subsystem spec
subsystem
design
engineering
doc tree, structure
overview draft
decomposition in subsystems draft
overview
decomposition in subsystems
performance budgets draft
performance budgets
functional model (design) draft
functional model (design) concept
function allocation draft
function allocation concept
control architecture draft
control architecture
SW architecture draft
functional model (design)
function allocation
SW architecture
Electrical architecture
handling interfaces
power, gas, water, etc budgets draft
mechanical layout budgets draft
costprice budget draft
consumable budget draft
costprice budget
consumable budget
interoperability design
safety analysis
reliability/uptime budget draft
diagnostic analysis
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power, gas, water, etc budgets
mechanical layout budgets
Gerrit Muller
safety design
reliability/uptime budget
diagnostic design
accessability
set up sequence
tolerance budget
cycle time budget
transport design
Definitions
PRS
Product Requirement Specification
What should the product be
Marketing
SPS
SDS
TPS
TAR
System Performance Specification
System Design Specification
Test Performance Specification
Test Acceptance Report
What will the product be
How will it be made
What and how will it be tested
Testresult
SE
SE
SE
SE
EPS
EDS
TPS
TAR
Element Performance Specification
Element Design Specification
Test Performance Specification
Test Acceptance Report
What
How
What and how will it be tested
Testresult
D&E
D&E
D&E
D&E
EPS, EDS, TPS are recursively applied from subsystem level to monodisciplinary module level
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Concurrent engineering, Integration
subsystem1 design
dynamical performance
subsystem2 design
imaging
•
•
•
•
•
Subsystem n design
Concurrent
engineering
overlay
metrology
levelling
Integration
prototypes
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Final
integration
Gerrit Muller
Moore’s law (or challenge?)
SIA
97
98
1994
roadmap
99
00
01
250
02
03
04
180
250
180
150
130
1998
revision
250
180
150
125
1999
proposal
250
180
130
90
180
130
06
130
1997
roadmap
leading
250
edge
customers
05
100
linewidth in nm.
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SIA
97
98
99
1994
roadmap
250
overlay
overlay
80
leading
250
edge
customers
overlay
80
00
180
60
01
02
180
130
35
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05
06
45
100
45
04
130
60
Rule of thumb: Process overlay = linewidth / 3
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03
Overlay budget
Dramatic
increase of
complexity!
2003:
35 nm
Reticle
15 nm
Process
Overlay
80 nm
Matched
Machine
60 nm
Process
dependency
sensor
5 nm
Lens
Matching
25 nm
Off axis
Sensor
repro
3 nm
Stage Al.
pos. meas.
accuracy
4 nm
Blue align
sensor
repro
3 nm
System
adjustment
accuracy
2 nm
Single
Machine
30 nm
Matching
Accuracy
5 nm
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Global
alignment
accuracy
6 nm
Off axis
pos meas
accuracy
4 nm
Stage
overlay
12 nm
Position
accuracy
7 nm
Stage grid
accuracy
5 nm
alignment
repro
5 nm
Metrology
stability
6 nm
Gerrit Muller
tracking
error X, Y
2.5 nm
tracking
error phi
75 nrad
Frame
stability
2.5 nm
Interferometer
stability
1 nm
tracking
error WS
2 nm
tracking
error RS
1 nm
Summary ASML developement strategy
• Concurrent engineering
• short development cycle time
• Networking
• market
• technology base
• flexibility
• System engineering
• modularity
• short integration
• Family concept
• upgradeability
• follow SIA roadmap
• reuse, risk reduction over generations
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Stellingen
• Multi disciplanary design process and skills required
• Most unforeseens show up during integration:
– force integration start as early as possible
– integration is always underestimated
• Manage the design and integration by a few key
parameters,
– however watch out for sub - optimization
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