Transcript Interrupts

Interrupts, and Low-Power Modes
Interrupts
They are like functions but with the critical distinction that they are requested by
hardware at unpredictable times rather than called by software in an orderly
manner. A periodic interrupt should be highly predictable in real time, but this is not
apparent to the CPU. Interrupts are commonly used for a range of applications:
 Urgent tasks that must be executed promptly at higher priority than the main code.
 Infrequent tasks, such as handling slow input from humans. This saves the overhead
of regular polling.
 Waking the CPU from sleep. This is particularly important in the MSP430, which
typically spends much of its time in a low-power mode and can be awakened only by
an interrupt.
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Interrupts
The code to handle an interrupt is called an interrupt handler or interrupt service
routine (ISR). It looks like a function but there are a few crucial modifications. The
feature that interrupts arise at unpredictable times means that an ISR must carry
out its action and clean up thoroughly so that the main code can be resumed
without error—it should not be able to tell that an interrupt occurred.
 Interrupts can be requested by most peripheral modules and some in the core of
the MCU, such as the clock generator. Each interrupt has a flag, which is raised (set)
when the condition for the interrupt occurs. For example, Timer_A sets the TAIFG
flag in the TACTL register when the counter TAR returns to 0. Each flag has a
corresponding enable bit, TAIE in this case. Setting this bit allows the module to
request interrupts.
 Most interrupts are maskable, which means that they are effective only if the general
interrupt enable (GIE) bit is set in the status register (SR). They are ignored if GIE is
clear. Therefore both the enable bit in the module and GIE must be set for
interrupts to be generated. The nonmaskable interrupts cannot be suppressed by
clearing GIE.
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Interrupts
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The MSP430 uses vectored interrupts, which means that the address of each ISR—its
vector—is stored in a vector table at a defined address in memory. In most cases
each vector is associated with a unique interrupt but some sources share a vector.
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Each interrupt vector has a distinct priority, which is used to select which vector is
taken if more than one interrupt is active when the vector is fetched. The priorities
are fixed in hardware and cannot be changed by the user. They are given simply by
the address of the vector: A higher address means a higher priority.
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The reset vector has address 0xFFFE, which gives it the top priority, followed by
0xFFFC for the single nonmaskable interrupt vector. The vectors for the maskable
interrupts depend on the peripherals in a particular device and are listed in a table
of Interrupt Vector Addresses in the data sheet. As an example, the vector for the
address 0xFFF2 has a higher priority than the shared vector of address of 0xFFF0.
Table -- Interrupt Sources, Flags, and Vectors
Interrupts
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Interrupts must be handled in such a way that the code that was interrupted can be
resumed without error. This means in particular that the values in the CPU registers
must be restored.The hardware can take two extreme approaches to this:
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Copies of all the registers are saved on the stack automatically as part of the
process for entering an interrupt. The disadvantage is the time required, which
means that the response to an interrupt is delayed. An alternative is to switch to a
second set of registers.
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The opposite approach is for the hardware to save only the absolute minimum,
which is the return address in the PC as in a subroutine. This is much faster but it is
up to the user to save and restore values of the critical registers, notably the status
register.
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The MSP430 is close to the second extreme but stacks both the return address and
the status register. The SR gets this privileged treatment because it controls the lowpower modes and the MCU must return to full power while it processes the
interrupt. The other registers must be saved on the stack and restored if their
contents are modified in the ISR.
When an Interrupt Is Requested
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A lengthy chain of operations lies between the cause of a maskable interrupt and
the start of its ISR. It starts when a flag bit is set in the module when the condition
for an interrupt occurs. For example, TAIFG is set when the counter TAR returns to
0. This is passed to the logic that controls interrupts if the corresponding enable bit
is also set, TAIE in this case. The request for an interrupt is finally passed to the CPU
if the GIE bit is set. Hardware then performs the following steps to launch the ISR:
◦ Any currently executing instruction is completed if the CPU was active when the
interrupt was requested. MCLK is started if the CPU was off.
◦ The PC, which points to the next instruction, is pushed onto the stack.
◦ The SR is pushed onto the stack.
◦ The interrupt with the highest priority is selected if multiple interrupts are
waiting for service.
◦ The interrupt request flag is cleared automatically for vectors that have a single
source. Flags remain set for servicing by software if the vector has multiple
sources.
When an Interrupt Is Requested
◦ The SR is cleared, which has two effects. First, further maskable interrupts are
disabled because the GIE bit is cleared; nonmaskable interrupts remain active.
Second, it terminates any low-power mode.
◦ The interrupt vector is loaded into the PC and the CPU starts to execute the
interrupt service routine at that address.
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This sequence takes six clock cycles in the MSP430 before the ISR commences. The
position of SR on the stack is important if the low-power mode of operation needs
to be changed.
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The delay between an interrupt being requested and the start of the ISR is called
the latency. If the CPU is already running it is given by the time to execute the
current instruction, which might only just have started when the interrupt was
requested, plus the six cycles needed to execute the launch sequence. This should
be calculated for the slowest instruction to get the worst case. Format I instructions
take up to 6 clock cycles so the overall latency is 12 cycles. The time required to
start MCLK replaces the duration of the current instruction if the device was in a
low-power mode.
When an Interrupt Is Requested
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The delay varies on each occasion because the interrupt may be requested at
different points during an instruction, whose length may also differ. Thus there is no
fixed interval between the request of an interrupt and the start of its ISR.
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An interrupt service routine must always finish with the special return from interrupt
instruction reti, which has the following actions:
◦ The SR pops from the stack. All previous settings of GIE and the mode control
bits are now in effect, regardless of the settings used during the interrupt service
routine. In particular, this reenables maskable interrupts and restores the
previous low-power mode of operation if there was one.
◦ The PC pops from the stack and execution resumes at the point where it was
interrupted. Alternatively, the CPU stops and the device reverts to its low-power
mode before the interrupt.
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This takes a further five cycles in the MSP430. The stack is restored to its state
before the interrupt was accepted.
Interrupt FETCH EXECUTE CYCLE
Interrupt Service Routines
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Interrupt Service Routines in Assembly Language
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An ISR looks almost identical to a subroutine but with two distinctions:
◦ The address of the subroutine, for which we can use its name (a label on its first
line), must be stored in the appropriate interrupt vector.
◦ The routine must end with reti rather than ret so that the correct sequence of
actions takes place when it returns.
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The other change in the program is that interrupts must be enabled or nothing
happens.
Interrupt Service Routines
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Interrupt Service Routines in C
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An interrupt service routine cannot be written entirely in standard C because there
is no way to identify it as an ISR rather than an ordinary function. Some extensions
are therefore needed and these inevitably differ between compilers.
◦ Two additions are needed to the ISR.
◦ First is the #pragma line, which associates the function with a particular
interrupt vector.
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The second is the __interrupt keyword at the beginning of the line that names the
function. This ensures that the address of the function is stored in the vector and
that the function ends with reti rather than ret.
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An intrinsic function is needed to set the GIE bit and turn on interrupts. This is
called __enable_interrupt(), singular rather than plural.
Issues Associated with Interrupts
Follow a few simple rules to avoid some of the difficulties.
 Keep Interrupt Service Routines Short: Other interrupts, which may be urgent,
are disabled during an ISR unless you choose to allow nested interrupts. If lengthy
processing is necessary, do the minimum in the ISR and send a message to the main
function, perhaps by setting a flag. The main function can then do the timeconsuming work between interrupts.
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Configure Interrupts Carefully: Make sure that unwanted interrupts are disabled.
This should be the case by default and a problem is likely to arise only if an
interrupt has been used at one time but not required later. Sometimes the flag can
become set before interrupts are wanted so it should be cleared before the enable
bit is set. Do not set the GIE bit until you are ready to handle interrupts.
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Define All Interrupt Vectors: It is good practice for safety to fill all the defined
entries of the vector table, even for interrupts that are not used.
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The Shared Data Problem: It arises when variables are used both in the main
function and in ISRs.
Low-Power Modes of Operation
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The MSP430 was designed from the outset for low power and this is reflected in a
range of low-power modes of operation.
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Active mode: Nothing is turned off (except maybe individual peripheral modules).
No power savings. CPU, all clocks, and enabled modules are active. The MSP430
starts up in this mode, which must be used when the CPU is required. An interrupt
automatically switches the device to active mode.
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LPM0 - CPU and MCLK are disabled while SMCLK and ACLK remain active.
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LPM1 - CPU and MCLK are disabled, and DCO is disabled if the DCO is not used
for SMCLK.ACLK is active
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LPM2- CPU, MCLK, SMCLK, DCO are disabled.ACLK is active.
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LPM3 - CPU, MCLK, SMCLK, DCO are disabled,ACLK is active.
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LPM4 - CPU and all clocks disabled.
Low-Power Modes of Operation
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It is common to describe a device as sleeping when it is in a low-power mode,
although this is a little vague in the MSP430 with its range of modes. Similarly, waking
means that the device returns to active mode.
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Once parts of the microcontroller are shut off, they will not operate until
specifically turned on again. However, we can exit a low power mode (and turn
these parts back on), and interrupts are extremely useful in this respect.
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The location in SR is vital because it means that any low-power mode is suspended
automatically when an interrupt is accepted. The current SR is stacked and the SR is
cleared for the interrupt service routine, including the low-power bits (except
SCG0 in some families). The low-power mode is resumed at the end of the ISR
when SR is restored from the stack.
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We usually enter a low power mode with the interrupts enabled. If we don’t, we will
not be able to wake up the system.The x represents LPMs from 0 to 4.
__bis_SR_register(),
_BIS_SR (GIE | LPM3_bits)
Waking from a Low-Power Mode
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An interrupt is needed to awaken the MSP430. The processor handles an interrupt
from a low-power mode in almost the same way as in active mode. The only
difference is that MCLK must first be started so that the CPU can handle the
interrupt; this replaces the first step when the CPU is active, which is to complete
the current instruction. MCLK is started automatically by the hardware for servicing
interrupts and requires no intervention from the programmer. Remember that the
status register is cleared when an interrupt is accepted, which puts the processor
into active mode. Similarly, MCLK is automatically turned off at the end of the ISR if
the MSP430 returns to a low-power mode when the status register is restored.
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We must exit the low power mode in the interrupt handler. This is done with the
following code:
__bic_SR_register_on_exit()
Low Power Mode Savings