Transcript No Slide Title

Altera’s Innovative Intellectual
Property (IP) Overview
© 2008 Altera Corporation—Public
The Programmable Solutions Company®
Intellectual property (IP)
Programmable logic
devices (PLDs) and
ASICs
A key enabler for the devices
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
2
FPGA Trends—System Interconnect
FPGA
µP
I/O
IP
Memory
ASSP
1. Standard I/O protocols for easy
connection to other chips
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
3
FPGA Trends—Embedded Processing
FPGA
µP
µP
I/O
IP
Memory
DSP
processor
ASSP
2. Embedded µP and digital signal
processing (DSP) blocks for processing
and coprocessing
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
4
FPGA Trends—System Integration
Need to reduce
board size to meet form
factor requirements
Too expensive: need
to reduce cost
I/O
Flash
Obsolete in 2 years
and must support
for 7 years
CPU
Changing standard
requires new device:
redesign board
SDRAM
I/O
I/O
Marketing requires
new features to stay
competitive
I/O
I/O
I/O
DSP
FPGA
FPGA
CPU
DSP
CPU
3. Replace external devices
with programmable logic
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
5
16-week lead
time must qualify
2nd source
Altera IP Solutions Strategy

Focus in-house development on:
 High-speed I/O interconnect technologies
 PCI Express, Serial RapidIO® standard,
Ethernet, SerialLite II, memory controllers
 DSP applications
 Video and image processing and
general purpose
 Embedded market
 Nios® II embedded processors,
peripherals, and design environment

Leverage third-party partners for
additional products and expertise

Complete solutions
 Flexible, high-quality IP cores
 Proven validation using development kits
 Reference designs to kick-start system design

Interoperability testing for key I/O protocols
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
6
Altera IP Portfolio*
Processors and
peripherals
 32/16 bit
 Nios II embedded
processor
DSP

 SOPC Builder
peripherals

Filters and transforms
 Finite impulse response (FIR)
 Color space converter
 Fast Fourier transform (FFT)
 Scaler
 Cascaded integrator comb (CIC)
 2D FIR filter
Error correction and detection
 SRAM
 Viterbi
 SDR SDRAM
 Reed-Solomon
 Flash
 Turbo
 Timer

 UART
interface (SPI)
 Programmable I/O
Modulation and demodulation
 Numerically controlled oscillator
 Serial peripheral
(NCO)
 Digital video broadcast (DVB)

 MPEG 2/4 CODECs
Video and image processing
 H.264 decoder
 JPEG encoder/decoders
* Includes partner IP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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 2D median filter
 Line buffer compiler
 Gamma corrector
 Chroma resampler
 Deinterlacer
 Alpha blending mixer
 Clocked video input
 Clocked video output
 Frame buffer
 Clipper
 Color frame sequencer
Altera IP Portfolio* (Continued)
Memory and memory
controllers
Interface protocols

Communications

 Packet over SONET
(POS) PHY 2/3 and SPI
4.2
 8B / 10B
 Utopia
 Cyclical redundancy check
(CRC)

media access control
(MAC) and physical
coding sublayer (PCS)
 10-Gbps MAC and PCS
 1588 industrial Ethernet
 Any speed MAC

 RapidIO standard
 HyperTransport™
technology
 SerialLite II

PCI


Serial
 USB 2.0 function
 I2C

Direct memory access
(DMA)
 DMA controller
 Scatter gather DMA
 32-/64-bit PCI
 PCI-X
 PCI Express /1, /4, /8
Ethernet
 10/100/1000 Mbps
High speed
Video
 Serial digital interface
(SDI)
 Asynchronous serial
interface (ASI)
* Includes partner IP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
8
SDRAM
 DDR / DDR2 SDRAM
controllers
 DDR / DDR2 / DDR3
SDRAM highperformance controllers
 RLDRAMII controller
 QDR II controller
PCIe Hard IP - Value Proposition


FPGA industry’s 1st 40-nm FPGA with PCI Express Gen2
support
Cost
 ~0 LEs used
 $0 list price

Ease of use
 No separate licensing required
 Significantly reduced compile times
 Equivalent to ~12K – ~20K LEs
 Exact numbers available at customer beta
 Significant power savings as compared to soft IP solution

Low risk
 2nd generation FPGA with PCIe Gen2 support
 4th generation FPGA with support for PCIe
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
9
Complete Solutions
Intellectual property (IP)
 Encrypted source code
 Testbench
 Documentation
Software tools



Reference designs and
design examples
Development kits
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
10
Quartus® II
software
SOPC Builder
DSP Builder
World-Class Third-Party IP Partners
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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System Integration
Create design blocks
Integrate system
Model-based design
IP
‘C’-based design
entity par_fir is
port (
io0_gpo : out std_logic_vector(15 downto 0);
io0_gpi : in std_logic_vector(15 downto 0);
clock : in std_logic;
reset : in std_logic
);
end entity;
HDL Entry
Embedded software development
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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Including
Altera Development Kits
 Focus
on quality and completeness
 All boards are fully tested and
verified before shipment
 Accompanied by accurate
technical documentation
 Complete
design environment
 Board with featured Altera® device
 Quartus II software (development kit edition)
 Altera IP library for free




hardware evaluation
Kit CD with reference designs and utilities
Documentation
Schematics/board layout files
Cables and accessories as necessary
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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It’s in
the box!
Ease of Use
© 2008 Altera Corporation—Public
Customer Expectations from IP

Works functionally

Meets performance
requirements in real designs

Area-efficient

Other deliverables
 Quality documentation
 Example design
 Test bench
 Software drivers and
protocol stacks
 Simulation models
 Hardware test platform

Quality support
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
15
FPGA
IP
Altera IP

Optimized for latest device families

Easier migration across device
families via cross-platform support

VHDL and Verilog support

Intuitive, easy-to-use GUI for core
configuration/parameterization

Shares release schedule with
Quartus II software
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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Interoperability Is Required

Proactive I/O protocol compliance and
interoperability testing
 PCI Express
 Ethernet
 Serial RapidIO (SRIO) standard

Interoperability at industry-standard
forums
 PCI-SIG-compliance workshops
 Ethernet University of New
Hampshire (UNH) validation
 Lab testing for RapidIO standard

Additional interoperability with ASSP,
DSP, and processor devices
 PCI Express, SRIO switches
 DSP processors
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
17
Typical IP Costs
Planning
Register transfer
level (RTL) coding
Verification
Enhancements*
Documentation
Hardware platform
Hardware testing
GUI
QA
Release
Total cost: $1.1M
Time to develop: 1 to 1.5 years
Marketing
Support
* Yearly costs
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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Altera’s Investment in IP

Geographically dispersed
organization
Marketing
 Centers of expertise (UK, San
Jose, Santa Cruz, and Penang)

> 154 staff members
Support
Engineering
(new)
 IP development engineers
 Software engineers
Documentation
 Technical writers
 Quality assurance and training
 Infrastructure and
packaging tools
 Application support engineers
 Product planning
 Product marketing

Software tools
Nios II
embedded
processor
engineering
Annual spending is ~9% of R&D
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
19
Engineering
(maintenance)
Worldwide IP Centers
San Jose, CA
• PCI Express
• RapidIO standard
• SerialLite II
• QA
Santa Cruz, CA
• Nios II embedded processor
• Nios C-to-H Compiler (C2H)
High Wycombe, UK
• DSP
• System solution engineering
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
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Penang, Malaysia
• Ethernet
• PCI
• Memory controllers
Application Examples
© 2008 Altera Corporation—Public
DSP in FPGA: Video Conferencing
Video
Audio
Deinterlacer
Spatial
noise
reduction
Audio
CODEC
CSC
Scaler
Audio
mixing
Multichannel
audio
decode
Alpha
blending
for OSD
PIP
mixer
Polycom VXS 8000
Altera IP
3rd-party or customer-proprietary IP
DSP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
22
ENCODER
ENCODER
Encoder
TCP/IP
stack
Multichannel
decode
Network
DSP in FPGA: Wireless Basestation
Power
amplifier
(PA)
Low-noise
amplifier
(LNA)
A/D
D/A
Digital I/F
DUC/DDC
DPD
CFR
Baseband processing
Rel 6/LTE/WiMAX
Glue logic
Glue logic
RF card
Host
CPU
Control
logic
Multiplexer/
demultiplexer
Host
µP
IP
proc
Channel card
Clock
generator
Switch
I/F
GPS
receiver
IP/ATM
interface
Glue logic
Glue logic
Control card
Timing
card
Switch card
Altera FPGA applications
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
23
BSC/RNC
interface
Gigabit Ethernet in FPGA: Multi-Port Switches

Flexible Altera Ethernet solution
 Target MAC for both transceiver and non-transceiver FPGAs
 Triple-speed operation (10/100/1000 Mbps) with auto-negotiation ensures
smooth data rate upgrades
10/100 MAC
Gigabit MAC
Switch core
Atlantic interface
MI /GMII
or SGMII
Atlantic™ interface
10/100 MAC
10 / 100 / 1000
MAC
Altera IP
3rd-party or customer-proprietary IP
Content courtesy of IP partner: MoreThanIP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
24
Serial
peripheral
interface
(SPI) 4.2
master
10-Gigabit Ethernet in FPGA
Line-Side Application
XFI
GbE
MAC
10-GbE
MAC
XFP
XAUI
XCVR
XFP
GbE
MAC
GbE
MAC
SFP
SFP
SFP
SFP
SFP
SFP
Altera IP

3rd-party or customer-proprietary IP
High-end server add-in cards
 Examples: multi-source data capture, TCP/IP offload, pre-buffering, custom processing, redundant
XAUI ports
Data plane endpoint
 Backplane interconnect
 High-end performance

Content courtesy of IP partner – MoreThanIP, Altera preferred partner for 10G MAC
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
25
PCI Express in FPGA
Endpoints, Bridges, and Switches

PCIe x4
Endpoints
 Memory controller
 Gigabit Ethernet (GbE), Fibre Channel, etc.
 Proprietary

Non-transparent bridge
 PCI, PCI-X

PHY
x4
Memory
Non-transparent switch
PCI
 Avalon® interface
PHY
x1
PCIe x4
Legacy
ASSP
PH
Y
PCIe x1
Avalon bridge
Avalon
Legacy
ASSP
ASSP
XXXXXXXXXXXXXX
PCIe x1
GbE
MAC
PCI
Memory
controller
GbE
Avalon
bridge
Altera IP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
26
Serial RapidIO Standard in FPGA
Bridges and Custom Endpoints
CPRI,
PCI,
PCI Express,
Ethernet
Serial RapidIO standard

Bridges
 PCI, PCI Express, Common
Public Radio Interface
(CPRI), Open Base Station
Architecture Initiative
(OBSAI), Ethernet, etc.
Memory

Custom endpoints
 Nios® II control plane
CPU
SRIO
switch
DSP
ASSP
processing
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
27
Serial RapidIO Standard in FPGA (2)
Multiprocessing System
 FPGA-based switch fabric
DSP
DSP
SRIO switch
DSP
DSP
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
28
Embedded Design with Nios II Embedded
Processor

Processing power
is ideal for:
 Automotive
 Industrial
 Access communications
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
29
Getting Started
© 2008 Altera Corporation—Public
Core Delivery

Delivered and installed as part of Quartus II
software beginning with v8.0 release

Web download from www.altera.com
 Included with both Subscription and Web Edition
versions of Quartus II software

After installation, cores can be selected within
Quartus II software and SOPC Builder

3rd-party IP is delivered upon request by
Altera partners
 Web product page has automated request form
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
31
IP Deployment Flow
Install
Parameterize
Real-time
logic simulation
VHDL and Verilog
Altera IP design flow
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
32
Hardware
evaluation
Licensing Altera IP

Perpetual-use licenses for production designs
 Royalty-free license grant
 One-year renewable maintenance, upgrades, and support
 Floating or node-locked licenses
 Migrate to Altera HardCopy® devices for no additional fee

Corporate and site licenses can be established to meet
an individual company’s needs
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
33
Summary

Altera development is focused on:
 High-speed I/O interconnect
 DSP
 Embedded technologies


Altera invests in producing complete,
easy-to-use solutions
3rd-party partner products expand
Altera portfolio and expertise
Enabling faster time-to-market
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
34