Transcript Signal Synthesis Products

The World Leader in High-Performance Signal Processing Solutions
Design a Clock Distribution for a
WCDMA Transceiver System
CSNDSP 2006
Session: B.11 Systems - Simulators
Presenter: Dimitrios Efstathiou
July 20th, 2006
In this presentation we will cover
 Where
we need Clock Distribution
Devices?
 Clock Design for a WCDMA
Transceiver System
 Introduction to ADIsimCLKTM
 ADIsimCLKTM Results versus Lab
measurements
2
Telecom Infrastructure
ATM Based Network
IP Core Network (IPv6,
MPLS)
3G Macro
2G Macro
3
Solution to save cost, board space
Integrated Circuit Solution in one small package
U2
Divide by 2
LVPECL
U1
1:4 Fanout
Buffer
LVPECL
Fanout
4
U3
Divide by 4
LVPECL
U6
LVPECL to
CMOS
U4
Divide by 8
LVPECL
U5
Delay 1-10ns
LVPECL
U7
LVPECL to
CMOS
Dividers
Delay
Logic
Translation
Application – Wireless Transceiver Card
ADC
Clock to A-D Converters
ADC
ADC
User’s
Reference
Clock
TRX Cards
Transmitter/Receiver
Clock Distribution IC
Critical Clock Functions on Transceiver Card:
• clean-up jitter on user’s input reference
• up-convert user reference frequency to highest
frequency needed, usually driven by DAC clock
requirements
• generate multiple frequencies for Rx & Tx
• provide low jitter clocks for data converters
• generate mix of LVPECL, LVDS, CMOS clocks
• adjust phase or delay between clock channels
• offer isolation between clock channels
5
Clock to
Digital Chips
ADC
DDC or
ASIC
DUC or
FPGA
DAC
Clock to D-A Converters
DAC
Transceiver clock design using ADIsimCLK™
AD9779
Carrier 1
I/Q
Tx
Baseband Carrier 2
I/Q
I-channel
AD6633
DUC
Q-channel
DAC 1
FPGA
DPD
DAC 2
Auxilary
temperature
measurement
ADC
LVPECL
307.20 MHz
LVDS
614.40 MHz
19.20 MHz
OUT6
OUT0
AD9215
LVEPCL
19.20 MHz
AD9510
OUT5
Carrier 1
I/Q
Rx
Baseband
Carrier 2
I/Q
OUT7
OUT1
OUT4
CMOS
30.72 MHz
6
To reconstruction
filters and
modulator
Imaginary
614.40 MHz
CMOS
76.80 MHz
Real
OUT2
OUT3
LVPECL
153.60 MHz
LVDS
102.40 MHz
AD9430
LVPECL
102.40 MHz
AD6636
DDC
AD9445
Receiver path
from Mixer
Carriers 1 & 2
Observation path
down-converted from
Power Amplifier
Carriers 1 & 2
A Clock Distribution Device with
integrated PLL
VCO
LF
7
ADC Output clocked by AD9510
AD9779
Real
Carrier 1
I/Q
Tx
Baseband
I-channel
Carrier 2
I/Q
AD6633
DUC
Q-channel
DAC 1
To reconstruction
filters and
modulator
FPGA
DPD
DAC 2
614.40 MHz
Auxilary
temperature
measurement
ADC
CMOS
76.80 MHz
Imaginary
LVPECL
307.20 MHz
LVDS
614.40 MHz
19.20 MHz
OUT6
OUT0
AD9215
LVEPCL
19.20 MHz
AD9510
OUT1
OUT4
OUT5
CMOS
30.72 MHz
Carrier 1
I/Q
Rx
Baseband
OUT7
OUT2
OUT3
LVPECL
153.60 MHz
LVDS
102.40 MHz
AD9430
LVPECL
102.40 MHz
AD6636
DDC
AD9445
Observation path
down-converted from
Power Amplifier
Carriers 1 & 2
Receiver path
from Mixer
Carriers 1 & 2
Carrier 2
I/Q
SNR from Jitter
120
SNR (dB)
110
100
90
80
70
60
50
1M
8
10M
100M
1G
IF Frequency (Hz )
DAC Output clocked by AD9510
AD9779
Carrier 1
I/Q
Tx
Baseband
Carrier 2
I/Q
I-channel
AD6633
DUC
Q-channel
FPGA
DPD
DAC 2
Auxilary
temperature
measurement
ADC
LVPECL
307.20 MHz
LVDS
614.40 MHz
19.20 MHz
OUT6
OUT0
AD9215
LVEPCL
19.20 MHz
AD9510
OUT5
Carrier 1
I/Q
Rx
Baseband
Carrier 2
I/Q
OUT7
OUT1
OUT4
CMOS
30.72 MHz
9
To reconstruction
filters and
modulator
Imaginary
614.40 MHz
CMOS
76.80 MHz
Real
DAC 1
OUT2
OUT3
LVPECL
153.60 MHz
LVDS
102.40 MHz
AD9430
LVPECL
102.40 MHz
AD6636
DDC
AD9445
Receiver path
from Mixer
Carriers 1 & 2
Observation path
down-converted from
Power Amplifier
Carriers 1 & 2
ADIsimCLK™
ADIsimCLK is a powerful and
flexible tool. It can help a user
design high performance clocking
systems using low-jitter clock
chips.
ADIsimCLK phase noise
simulations match the product
information sheet typical values
within ~2 dB.
Timing simulations align well with
product information sheet typical
values.
10
Select the ADI clock chip: AD9510
see product
information
sheet
Clock
Device
11
specs
Select the configuration:
Use integrated PLL
Default Configuration
Use integrated PLL
Use external filter
Use clock
distribution
circuit only
12
VCO Selection:
VCO
library
13
see
product
information
sheet
PLL Loop Filter Selection:
Loop bandwidth and phase margin
Passive and active filters
14
Clock Distribution Configuration:
Enable Outputs
Eight clock
outputs
Configuration
per output
15
Clock Distribution Configuration:
Configure Output
Divider value
Output Freq.
Integration
Interval
16
Results Page: OUT2 (LVPECL)
17
Another Design Example: Clock Distribution
circuit only
18
ADIsimCLK versus Lab measurements
OUT3 Phase Noise (LVPECL 61.44 MHz)
-130
OUT5 Phase Noise (LVDS, 122.88 MHz)
AD9510 Datasheet
ADIsimCLK
-135
-115
AD9510 Datasheet
ADIsimCLK
-125
-140
Phase Noise Density (dBc/Hz)
Phase Noise Density (dBc/Hz)
-120
-145
-150
-155
-130
-135
-140
-145
-150
-160
-155
-165
1
10
19
2
10
3
10
4
5
10
10
Frequency Offset (Hz)
6
10
7
10
-160
0
10
2
10
4
10
Frequency Offset (Hz)
6
10
8
10
In summary we discussed
A
Clock Design Strategy for a
WCDMA Transceiver System
 ADIsimCLKTM: A Clock
generation and distribution
simulator
 Download
this free tool at
www.analog.com/ADIsimCLK
Thank you!
20
PLL Frequency Set-up:
PLL
Frequency
PFD
Frequency
21
Input Clock Selection:
Choose an input
Reference
frequency.
22
Information on the PLL: Frequency Domain
23
Phase noise and timing jitter at a divider’s input
and output
Root mean square (rms) value
of integrated phase noise
(units in radians)
f2
  rms 

S ( f m ) dBc / Hz (sin gle side )
10
2 10
(1)
f1
 rms  2    T jitter(rms )  Fout
Fin
N

out
  rms
(3)
2    Fout
-130
 rms  2    T jitter  Fout
T jitter( rms ) (sec) 
  rms
-125
(4)
  rms
2    Fo
Fin  rms ,in
 2    T jitter 

N
N
  rms ,i

N
F
2    IN
N

  rms ,i
2    FIN
(6)
(5)
Phase Noise Density (dBc/Hz)
Fout 
T jitter( rms ) (sec) 
(2)
-135
S ( f m )
-140
-145
-150
-155
-160
-165
2
10
3
10
f1
4
5
6
10
10
10
fm (Hz) frequency offset
7
Transition of a divider’s output is re-sampled with a transition of its input, a jitter of value Tjitter occurring at
the input will cause the same amount of jitter at the output.
24
8
10
10
f2
Get the results: schematic
25
Get the results: text report
26
Get the results: timing
Timing Diagram
CLK 2
FP GA
0.11 ns
RE F
A DC1
A DC2
A DC3
A S IC2
A S IC1
DA C
0
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Time (ns)