Transcript Dr. Andrei Grebennikov

LECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGN
4.1. Overdriven Class B
4.2. Class F circuit design
4.3. Inverse Class F
4.4. Class E with shunt capacitance
4.5. Class E with parallel circuit
4.6. Class E with transmission lines
4.7. Broadband Class E circuit design
4.8. Practical high efficiency RF and microwave
power amplifiers
1
4.1. Overdriven Class B
In overdriven Class B, voltage and current waveforms have increased
amplitudes with the same peak values as in conventional Class B
v
V0  Vcc
for DC voltage:
Vcc(1+k)
for fundamental voltage :
2Vcc
V1 

2 Vcc  1

 cos1 
  sin1

for odd voltage components, n = 3, 5, … :
Vcc
Vn 
0

1
2
-1 +1 2-1
t
2 Vcc  sin 1  n1  sin 1  n1 
2cosn1 



1  n sin1
  1  n  sin1
n

for even voltage components, n = 2, 4, … :
i
for DC current:
kIs
I0 
for fundamental current:
Is
Vn  0
Is  
 
 1  tan 1 

  2
2

I s  1

I1 
 cos1 

  sin1

for odd current components, n = 3, 5, … :
0
1
-1 
2
t
In 
I s  sin 1  n1  sin 1  n1 
2cos n1 



1  n sin1
  1  n  sin1
n

2
4.1. Overdriven Class B
2

Vcc I s  1
V1 I1

P1 

 cos1  - fundamental output power
2 
2
  sin1

V I 
  - DC output power
P0  V0 I 0  cc s 
 1  tan 1 
  2
2
Out-of-band impedances :
Zn 
2 Vcc
 RL ,
Is
Zn  0 ,
for odd n
for even n
where RL is load resistance
1
1
1
 lim
 lim
1
For lim
 0 sin
 0 sin 
 0 cos 
1
1
1
1
1
1
Collector efficiency
:
 1


 cos1 
P
1 sin1

  1  
P0      tan1
1
2
2
 
8

2
2
 81%
- maximum collector efficiency for square voltage and current waveforms
Analyzing  on extremum gives  = 88.6% for optimum angle  1= 32.4
3
i
4.2. Class F circuit design
Is
0

t
2
v
Vcc(1+k)
Is
- fundamental current component
2
V1 
4 Vcc - fundamental voltage component

when 1 0
P1 
2Vcc
Vcc
0
I1 
1
 -1 
t
2
Vcc I s
- fundamental output power

V I
- DC output power
P0  cc s

P
  1  100% - collector efficiency
P0
Harmonic impedance conditions:
Ideal voltage and current waveforms:
i
v
2Vcc
Is
Vcc
0

2
t
0

2
t
8 Vcc

Z

R

1
L

 Is

 Z n  0 for even n
 Z   for odd n
 n

4
4.2. Class F circuit design: quarterwave transmisssion line
Cb
Vcc
Assumptions for transistor:
• ideal switch:
no parasitic elements
x
l
vinc
iinc
/4
i
iT
vref
iref
0
• half period is on,
half period is off:
50% duty cycle
iR
L0
Assumptions for load:
C0
R
v
vin
i(t) = IR sint
• purely sinusoidal current:
ideal L0C0-circuit tuned at
fundamental
- load current
v(t) = 2Vcc – v(t + ) - collector voltage
iT(t) = iT(t + ) = IRsint - transmission-line current
i(t) = IR(sint + sint) - collector current
5
4.2. Class F circuit design: quarterwave transmission line
iR/I0
1.5
collector current
consisting of fundamental
and even harmonics
1.0
0.5
t, 
0
60
120
180
240
300
-0.5
i/I0
-1.0
3.0
-1.5
2.0
sinusoidal load
current
1.0
0
v/Vcc
0
60
120
180
240
300
t, 
2.0
1.5
1.0
transmission-line current
consisting of even harmonics
0.5
0
0
60
120
180
240
300
t, 
iT/I0
1.5
rectangular collector
voltage
1.0
0.5
0
0
60
120
180
240
300
t, 
6
For maximally flat
waveforms:
4.2. Class F circuit design
optimum
values:
collector current
collector voltage
v/Vc
i/I0
n = 1, 3
c
2.5
2.0
V1 
9
Vcc
8
optimum
values:
n = 1, 2
2.0
1.5
1.5
1.0
I1 
4
I0
3
I2 
1
I0
3
1.0
1
V3  Vcc
8
0.5
0.5
/2
0
3/2


0
/2

3/2


3/2

i/I0
v/Vcc
n = 1, 2, 4
n = 1, 3, 5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
/2
0


3/2
0
/2
Current harmonic components
Voltage harmonic components
1
1, 3
1, 3, 5
1, 3, 5, 7
1, 3, 5, …, 
1
1/2 =0.500
9/16 = 0.563
75/128 = 0.586
1225/2048 = 0.598
2/ = 0.637
1, 2
2/3 = 0.667
3/4 = 0.750
25/32 = 0.781
1225/1536 = 0.798
8/3 = 0.849
1, 2, 4
32/45 = 0.711
4/5 = 0.800
5/6 = 0.833
245/288 = 0.851
128/45 = 0.905
1, 2, 4, 6
128/175 = 0.731
144/175 = 0.823
6/7 = 0.857
7/8 = 0.875
512/175 = 0.931
1, 2, 4,…, 
/4 = 0.785
9/32 = 0.884
75/256 = 0.920
1225/4096 = 0.940
1 = 1.000
7
4.2. Class F circuit design: second current and third voltage
harmonic peaking
Vcc
Output susceptance:
Cbypass
Load
network
ImYout   j Cout
1   2 L2C2
 j
 L1 1   2 L2C2   L2


Three harmonic impedance conditions:
C2
L2
ImY1 = 0
ImY2 = 
ImY3 = 0



 1   02 L1Cout 1   02 L2C2   02 L2Cout  0 ,

L1 1  4 02 L2C2  L2  0 ,

 1  9 2 L C 1  9 2 L C  9 2 L C  0 ,
0 1 out
0 2 2
0 2 out






L1
S21 simulation (f0 = 500 MHz)
S21, dB
Rout
Cout
Yout
To output
matching
circuit
Circuit parameters
1
5
12
L1 
,
L

L
,
C

Cout
2
1
2
6 o2Cout
3
5
0
1
0
2
0
3
0
4
0 0
0.5
1.0
1.5
2.0
f, GHz
8
4.2. Class F circuit design: even current and third voltage
harmonic peaking
Vdd
Load
network
Harmonic impedance conditions:
Cbypass
ImY1 = 0
1
ImYeven = 
3
ImY3 = 0
2
To output
matching
circuit
Cout
Rout
Yout
S21 simulation (f0 = 500 MHz)
S21,
0 dB
10
Circuit parameters:
1 

2
,
3 
20

6

1
1
 2  tan1 
3
 3Z 0 Cout
30



40
0
0.5
1.0
1.5
2.0
f, GHz
Requires additional impedance
matching at fundamental
9
4.2. Class F circuit design
Class F power amplifier with lumped elements
24 V
Drain voltage and current waveforms
100 pF
1.5 k
f0 = 500 MHz
vd, V
4.5 nH
10 pF
300 
500 
2 pF
id, A
40
0.7
20
0
3.6 nH
3.5 pF
15 nH
25 nH
Pout
Pin
6 pF
1.1 pF
0
gain, dB
efficiency, %
22
100
1
80
20
2
60
1
40
18
16
2
20
14
0
12
10
12.5
15
17.5
20
22.5
Pin, dBm
1
0
Output
matching
2
3
t, nsec
LDMOSFET:
gate length 1.25 um
gate width 7x1.44 mm
1 - inductance Q-factor = 
efficiency > 82%,
linear power gain > 16 dB
2 - inductance Q-factor = 30
efficiency < 71%,
linear power gain > 14 dB
10
4.2. Class F circuit design
Class F power amplifier with transmission lines
24 V
Drain voltage and current waveforms
f0 = 500 MHz
100 pF
1.5 k
Output
matching
300 
50 
75
2.5 pF
500 
30 
90
30 
12
50 
45
Pin
id, A
vd, V
50 
73
efficiency, %
4.5 pF
50 
13
30 
30
gain, dB
100
22
80
20
40
1
20
0
Pout
0
1
2
3
t, nsec
LDMOSFET:
gate length 1.25 um
gate width 7x1.44 mm
60
18
T-matching circuit for output
impedance transformation
40
16
Output power - 39 dBm or 8 W
20
14
12
0
10
12.5
15
17.5
20
22.5
Pin, dBm
Collector efficiency - 76%
Linear power gain > 16 dB
11
4.3. Inverse Class F
Concept of inverse Class F mode was introduced for low voltage power
amplifiers designed for monolithic applications (less collector current)
Dual to conventional Class F
with mutually interchanged
current and voltage
waveforms
i
2I0
I0
0

2
t
4I 0

- fundamental current
Vs

 Vcc - fundamental voltage
2
2
VI
P1  s 0
- fundamental output power

VI
P0  Vcc I 0  s 0
- DC output power

V1 
 
P1
 100% - ideal collector efficiency
P0
Harmonic impedance conditions:
v
Vs
0
I1 

2
t
 Vs

Z

R

1
L

8 I0

 Z n  0 for odd n
 Z   for even n
 n

12
4.3. Inverse Class F
Optimum load resistances for different classes
Load resistance in Class B :
RL( B) 
Load resistance in Class F :
( F)
L
Load resistance in
inverse Class F :
Load resistance in
inverse Class F is
the highest
(1.6 times larger than
in Class B)
R
Vcc
I1
4 Vcc
4 (B)

 RL
 I1

RL(invF) 
 Vcc
2 I1

2
8
RL(F) 

2
RL(B)
Less impedance
transformation ratio
and easier matching
procedure
13
4.3. Inverse Class F: second current and third voltage
harmonic peaking
Vdd
Harmonic impedance conditions:
Cbypass
Load
network
ImY1 = 0
1
ImY2 = 0
3
ImY3 = 
2
To output
matching
circuit
Cout
Rout
S21 simulation (f0 = 500 MHz)
S21, dB
0
10
Circuit parameters:
1 

3
,
3 

4
1


1
1


1
 2  tan  2Z 0 Cout 
 
2
3  

20
30
40
0
0.5
1.0
1.5
Requires additional impedance
matching at fundamental
2.0
f, GHz
14
4.3. Inverse Class F
Inverse Class F power amplifier with transmission lines
24 V
f0 = 500 MHz
Output
matching
300 
2.5 pF
500 
30 
60
30 
44
50 
45
Pin
id, A
vd, V
100 pF
1.5 k
50 
75
Drain voltage and current waveforms
50 
63
50 
45
50 
22
60
2.1
40
1.4
20
0.7
0
0
6 pF
Pout
-20
gain, dB
efficiency, %
100
22
80
20
60
18
40
16
0
1
2
3
-0.7
t, nsec
LDMOSFET:
gate length 1.25 um
gate width 7x1.44 mm
T-matching circuit for output
impedance transformation
Output power - 39 dBm or 8 W
20
14
0
12
10
12.5
15
17.5
20
22.5
Pin, dBm
Collector efficiency - 71%
Linear power gain > 16 dB
15
4.3. Inverse Class F
Inverse Class F power amplifier with transmission lines
24 V
vd, V
f0 = 500 MHz
100 pF
1.5 k
Output
matching
300 
2 pF
30 
54
500 
6
40
4
20
2
0
0
30 
60
30 
62
50 
63
Pin
id , A
60
9 pF
50 
45
Pout
50 
83
-20
2
1
0
-2
3
t, nsec
24 V
efficiency, %
100 pF
1.5 k
300 
2 pF
Pin
30 
54
50 
63
500 
30 
65
30 
62
50 
45
gain, dB
100
22
80
20
60
18
40
16
20
14
9 pF
Pout
0
Load network with
output matching
0
5
10
15
20
25
12
Pin, dBm
16
4.4. Class E with shunt capacitance
L
RFC
vb
Vbe
C
Vcc
L0
C0
R
In Class E power amplifiers,
transistor operates as on-to-off
switch and ideal shapes of
current and voltage waveforms do
not overlap simultaneously
resulting in 100% efficiency
Unlike Class F power amplifiers analyzed in frequency domain as their
voltage and current waveforms contain either in-phase or out-of-phase
harmonics, Class E power amplifiers are analyzed in time domain as their
current and voltage waveforms contain harmonics having specified
different phase delays depending on load network configuration
Basic circuit of Class E power amplifier with shunt capacitance consists of
series inductance L, capacitor C shunting transistor, series fundamentally
tuned L0C0 resonant circuit, RF choke to supply DC current and load R
Shunt capacitor C can represent intrinsic device output capacitance and
external circuit capacitance
Active device is considered as ideal switch to provide instantaneous device
switching between its on-state and off-state operation conditions
17
4.4. Class E with shunt capacitance
RFC
I0
L0
L
iC
i
Optimum voltage
conditions across switch:
C0
iR
Vcc
v
C
R
vt   t 2  0
dvt 
 0
dt t 2
Idealized assumptions for analysis:
• transistor has zero saturation voltage, zero on-resistance, infinite offresistance and its switching action is instantaneous and lossless
• total shunt capacitance is assumed to be linear
• RF choke allows only DC current and has no resistance
• loaded quality factor QL of series fundamentally tuned resonant L0C0 circuit is infinite to provide pure sinusoidal current flowing into load
• reactive elements in load network are lossless
• for optimum operation 50% duty cycle is used
iR  t   I R sin  t    - sinusoidal current flowing into load
18
4.4. Class E with shunt capacitance
RFC
I0
L0
L
iC
i
Optimum voltage
conditions across switch:
C0
iR
Vcc
v
0  t  

R
C
- switch is on  iC t   C
dv t 
 0
d t
vt   t 2  0
dvt 
 0
dt t 2
it   I 0  I R sint    or using initial condition
when
  t  2
it   I R sint     sin 
I 0   I R sin 
- switch is off 
i0  0
it   0

iС t   I 0  I R sint   
t
1
IR


cost     cos  t   sin  
v t  
i

t
d

t



С
C 
C
2 
1 



tan


   32.482
From first optimum condition:
 
v  t  
I0 
3


 cos t  sin  t 
 t 
C
2
2

19
4.4. Class E with shunt capacitance
iR/I0
Optimum circuit parameters :
1.5
1
0.5
Load
current
0
60
-0.5
120
180
240
300
t

- series inductance
C  0.1836
-1.5
v/Vcc
3.5
3
2.5
2
Optimum phase angle at
fundamental seen by switch :
1.5
1
0.5
0
0
60
120
180
240
300
t
i/I0
2.5
Collector
current
R
1
- shunt capacitance
R
Vcc2
- load resistance
R  0.5768
Pout
-1
Collector
voltage
L  1.1525




CR
1  L 
1

  tan    tan 

L
R
1 


CR 

 I R

I1
2
L
R
1.5
1
V1
C
0.5
R

0
0
60
120
180
240
300
t
20
4.4. Class E with shunt capacitance
RFC
L0
L
Power loss due to non-zero
saturation resistance
C0
rsat
Vcc
R
C
Power loss due to finite
switching time
i
Non-ideal
switch
Pa 
a
i(2)

1
2
RFC
C
where
2 +1
L
Vcc
Nonlinear
capacitance
2
rsat
8 rsat Pout
Psat 

3
3 Vcc2
R
L0
 a2
12
 a  0.35 or 20
Only 1%
C0
R
For nonlinear capacitances
represented by abrupt
junction collector
capacitance with  = 0.5,
peak collector voltage
increases by 20%
21
4.5. Class E with parallel circuit
L0
L
vb
C
Optimum voltage
conditions across
switch:
C0
R
Vcc
iR  t   I R sin  t   
vt   t 2  0
dvt 
 0
dt t 2
- sinusoidal current in load
• basic circuit of Class E power amplifier with parallel circuit consists of
parallel inductance L supplying also DC current, parallel capacitor C shunting
transistor, series fundamentally tuned L0C0 resonant circuit and load R
• shunt capacitor C can represent intrinsic device output capacitance
and external circuit capacitance
• active device is considered as ideal switch to provide instantaneous
device switching between its on-state and off-state operation conditions
22
4.5. Class E with parallel circuit
iC
v
C0
L0
i
iL
Optimum voltage conditions
across switch:
iR
vt   t 2  0
L
R
C
dvt 
 0
dt t 2
Vcc
0  t  
- switch is on  vt   Vcc  vL t   0
it   iL t   iR t  
  t  2
- switch is off 
and
iC t   C
dv t 
 0
d t
Vcc
t  I R sin t     sin 
L
it   0

iC t   iL t   iR t 
dvt 
1
 Vcc  vt  d t   iL    I R sin t   
C


d t 
L 
t
under initial conditions
v   0
and
iL   
Vcc 
 I R sin
L
23
4.5. Class E with parallel circuit
d 2vt 
 LC
 vt   Vcc  LI R cos t     0 - second-order
2
d t 
differential equation
2
vt 
q2 p
 C1 cos qt   C2 sin qt   1 
cos t   
Vcc
1  q2
where
q  1/  LC ,
p 
LI R
Vcc
and coefficients C1 and C2 are defined
from initial conditions
To define three unknown parameters q,  and p, two optimum
conditions and third equation for DC Fourier component are applied
resulting to system of three algebraic equations:
vt   t 2  0
q  1.412
dvt 
 0
dt t 2
  15.155
1
Vcc 
2
2
 vt  dt
0
p  1.21
24
4.5. Class E with parallel circuit
iR/I0
Optimum circuit parameters :
Load current
1
0
t
240
120
L  0.732
3.5
Current through
capacitance
Collector
voltage
iC/I0
2.5
2
Optimum phase angle at
fundamental seen by switch :
1
0
t
180
- parallel inductance

0.685
- parallel capacitance
C 
R
Vcc2 - load resistance
R  1.365
Pout
-1
v/Vcc
R
t
0
180
-1
I 
  tan1  X   34.244
 IR 
I1
i/I0
Collector
current
2.5
iL/I0
3
1
0
Current through
inductance
IX
V1
1.5
180
t
0
-0.5
IR
C
L
VR
R

t
180
25
4.6. Class E with transmission lines: approximation
v/Vcc
Two-harmonic collector
voltage approximation
Optimum impedance at
fundamental seen by device :

Znet1  R 1  j tan49.052
3

2
• electrical lengths of transmission
lines l1 and l2 should be of 45° to
provide open circuit seen by device
at second harmonic
1
0
t

2
Cb
l2
Cout
RFC
RL
Vcc
Znet
Bipolar output
4
l1
MESFET output
S
3
l1
S
Cout
90 @ 2.7 GHz
Cb
l2
90 @ 1.8 GHz
• their characteristic impedances
are chosen to provide optimum
inductive impedance seen by
device at fundamental
RFC
Vcc
RL
• for three harmonic
approximation, additional open
circuit transmission line stub
with 90-degree electrical length
at third harmonic is required
( 1.5 GHz, 1.5 W, 90% )
26
4.6. Class E with transmission lines: approximation
Optimum impedance at
fundamental seen by device :
Transmission-line Class E power amplifier
with parallel circuit
L0

C0
Znet1  R / 1  j tan34.244

filter
C
TL
R
Cb
vin
Vcc
Parallel inductance is
replaced by transmission line
providing optimum inductive
reactance at fundamental :
Z0 tanθ  ωL
Impedance seen by
device at harmonics
Impedance seen by
device at fundamental
Znet
Znet
R
TL
C
where
L  0.732
R

Relationship between
optimum transmission line
and load parameters :
TL
C
R
tanθ  0.732
Z0
27
4.6. Class E with transmission lines: approximation
3.5 V
Cbypass
50 
12
Transmission-line Class E power
amplifier with parallel circuit :
example of load network of DCS1800
handset HBT power amplifier
30 , 8
50 , 16
10 pF
Collector voltage
vc/Vcc
off
on
on
3
2
1
Rout
5 pF
4 pF
50  0
0.0
0
Cout
0.2
0.6
0.8
1.0
t, nsec
Collector current
ic, A
Znet
0.4
3
• parameters of parallel
transmission line is chosen
to realize optimum inductive
impedance at fundamental
Znet(0)
2
1
0
-1
0.0
0
Znet(20)
Znet(30)
• output matching circuit consisting
of series microstrip line with two
parallel capacitances should provide
capacitive reactances at second and
third harmonics
0.2
0.4
0.6
0.8
t, nsec
1.0
Current flowing
through collector
capacitance
28
4.6. Class E with transmission lines: design example
1.71-1.98 GHz handset InGaP/GaAs HBT power amplifier:
two-stage MMIC designed in 2001
3.5 V
3.5 V
Short
mictostrip
line: 15
Vb1
Vb2
Bias
circuit
Bias
circuit
DCS1800/PCS1900:
Pout  30 dBm
PAE  51 %
Short
mictostrip
line: 15
WCDMA:
Pout = 27 dBm
ACPR = -37 dBc
PAE = 38 %
Pout
Pin
Shunt inductance:
bondwire
3x3mm
package
29
4.6. Class E with transmission lines: design example
Vg
28 V single-stage LDMOSFET
power amplifier module
1 k
W = 281.44 mm
L = 1.25 m
Z0 = 50 
 = 25
16 pF
9 pF
Pout
Pin = 1 W
LDMOS die
28 V
16 pF
Z0 = 50 
 = 30
Z0 = 50 
 = 40
9 pF
30 mm
15 mm
Bandwidth: 480-520 MHz
Output power: 20 W
Input
Gate bias
Drain supply
Output
Power gain: 15 dB
PAE: 67%
30
4.6. Class E with quarterwave transmission line
Vcc
Cb
Optimum voltage conditions
across switch:
vt   t 2  0
/4
iL
i
iC
v
C
iT
L0
C0
dvt 
 0
dt t 2
iR
L
vT
• sinusoidal load current
R
• 50% duty cycle
d 2iC t 
q2

iC t   I R sin t     0
2
2
d t 
boundary conditions:
iC t  t   2iR  
diC t 
V
 cc  I R cos 
d t  t 
L
p 
- second-order differential
equation
LI R
Vcc
q  1/  LC
q  1.649 p  1.302
  - 40.8
31
4.6. Class E with quarterwave transmission line
Optimum circuit parameters :
Load current
iR/I0
2.0
1.0
L  1.349
60
180
300
-1.0
-2.0
Collector voltage
v/Vc
3.5
iC/I0
c
Current through
capacitance
1.5
0
- series inductance

0.2725
- shunt capacitance
C 
R
Vcc2 - load resistance
R  0.465
Pout
t,
0
R
60
180
300
2.5
1.5
0
t,
t,
60
300
180
-1.5
Current through
transmission line
Collector current
i/I0
2.5
iT/I0
2.0
1.5
1.0
0
60
180
300
t,
0
60
180
300
t,
32
4.6. Class E with quarterwave transmission line
Optimum impedances at fundamental and
harmonics for different Class E load networks
f0
(fundamental)
Class E load network
2nf0
(even harmonics)
(2n+1)f0
(odd harmonics)
L
Class E with
shunt capacitance
Class E with
parallel circuit
C
R
L
C
C
R
C
C
L
C
L
L
Class E
with quarterwave
transmission line
C
C
L
C
R
33
4.7. Broadband Class E circuit design
Reactance compensation load network
C0
Device
L0
output
Z
in
Rout
C
R
L
Reactance compensation principle
Input load network admittance


1
1

Yin   j C 


j

L
R

j

L
0 


 02 
    1  2 
 

To maximize bandwidth:
d ImYin  
d
Xin
1
2

C 
0
1 - impedance
provided by series
L0C0 resonant circuit
 0  1 / L0C0
1
 2L

0
 0
2 L0
 0
2
R
Optimum circuit parameters using
equations for inductance L and
capacitance C in Class E mode
2 - impedance provided
by parallel LC
resonant circuit
• summation of reactances with opposite slopes results
in constant load phase over broad frequency range
L0  1.026
R

C0  1/ 2 L0
34
4.7. Broadband Class E circuit design
Double reactance compensation load network
C0
Device
To maximize bandwidth:
L0
dB
d
output
Y
in
Rout
C
C1
L
L1
  0
d 3B

d 3
0
  0
R
C1 R 2  L0
C  2  2
 0
 L
R2
1



 2
C1R 2  L0
C1R 2  L0 L0  2C1R 2 
2

 8 L0 C1 
  0
2
2
4
 L
R
R


1
Load network phase angle
, degree
Optimum circuit parameters using
equations for inductance L and
capacitance C in Class E mode
40
1
2
35
L0 
30
C1 
100
120
140
160
180
f, MHz
R

2
5 1
L0 3  5
R2
2
C0 
1
 2 L0
L1 
1
 C1
2
1 - single reactance compensation load network
2 - double reactance compensation load network
35
4.7. Broadband Class E circuit design
Broadband Class E power amplifier with double reactance compensation
10 nF
Drain voltage and current
waveforms
28 V
1.5 k
vd, V
300 
50 
f0 = 120…180 MHz
1 nF
Pin
80
1.5
60
1.0
40
0
0.5
10 nF
20 nH
Pin = 1 W
id, A
62 nH
64 nH
50 nH
10 pF
10 pF
20 pF
Pout
110 nH
10 pF
0
20
efficiency, %
gain, dB
76
1
74
10.5
2
72
10.0
0
0
3
6
-0.5
9
t, nsec
LDMOSFET:
gate length 1.25 um
gate width 7x1.44 mm
1 - drain efficiency > 71%
2 - power gain > 9.5 dB
70
9.5
68
100
120
140
160
180
f, MHz
Input power - 1 W
Input VSWR < 1.4
Gain flatness   0.3
36
4.8. Practical high efficiency RF and microwave power amplifiers
Typical bipolar RF Class F power amplifier
• zero-volt Class C biasing
Vcc
using RF choke
Cb
/4
L4
C1
Pin
• T-type input and output
matching circuits with
parallel capacitance
C3
L2
C2
L3
C4
Pout
• quarterwave
transmission line in
collector to suppress
even harmonics
• high-Q series LC circuit to provide high impedance
conditions for harmonics
Up to 90% collector efficiency for 10 W at 250 MHz
37
4.8. Practical high efficiency RF and microwave power amplifiers
Harmonic controlled MESFET microwave Class F power amplifier
Vg
• Class AB biasing with small
quiescent current
Vdd
Cb
Cb
R1
L1
l2
l1
Pin
50 
C5
C4
C2
ZS2
ZL2
Pout
50 
• T-type input and
output matching
circuits with parallel
capacitance
• using second harmonic
controlled circuits with series
50-ohm microstrip line and
capacitance each at device
input and output
Input second-harmonic termination circuit is required to provide input
quasi-square voltage waveform minimizing device switching time
74% power-added efficiency for 1.4 W at 930 MHz
38
4.8. Practical high efficiency RF and microwave power amplifiers
High power LDMOSFET RF Class E power amplifier
20 V
• Class B with zero quiescent current
• series inductance and ferrite 4:1
100 nH
transformer is required to match
device input impedance
MRF183
4:1
24 nH
12 nH
120 pF
Pout
50 
Pin
55 pF
100 pF
• quality factor of resonant circuit was chosen
to be sufficiently low ( 5 ) to provide some
frequency bandwidth operation and to reduce
sensitivity to resonant circuit parameters
• L-type output transformer
to match optimum 1.5-ohm
output impedance to 50-ohm
load
• required value of Class E shunt
capacitance is provided by device
intrinsic 38-pF capacitance and
external 55-pF capacitance
70% drain efficiency for 54 W at 144 MHz
39
4.8. Practical high efficiency RF and microwave power amplifiers
Low voltage fully integrated MESFET Class E power amplifier
1.2 nH
2.5 V
• Class AB with small quiescent current
1.5 pF
3.9 nH
3.7 nH
7.9 pF
3.7 nH
40 pF
40 pF
3.7 nH 7.7 pF
9.4 nH
10 pF
3.1 pF
Pin
50 
6.2 nH
Pout
8.1 pF
50 
5 nH
10 k
-1 V
-0.7 V
• Class E load network with optimum series
inductance and shunt capacitance
• T-type output matching circuit for
impedance transformation to 50-ohm load
• Class F interstage harmonic
controlled circuit using two LC
resonant circuits tuned on
fundamental and third harmonic
to approximate square-wave
driving signal
50% power-added efficiency for 24 dBm within 800-870 MHz
40
4.8. Practical high efficiency RF and microwave power amplifiers
225-400 MHz 28 V 20 W LDMOSFET Class AB power amplifier: simulations
28 V
Stability
100 pF
2.5 k
Pin = 1 W
30 pF
Z0 = 30 
 = 33
10 k
W = 281.44 mm
L = 1.25 m
75
100 pF
Z0 = 30 
 = 69
33 pF
Pout
Z0 = 30 
 = 41
45 pF
20 nH
75 pF
Power gain
gm = 0.6 A/V
fT = 4.5 GHz
8 pF
Power-added efficiency
14 dB
70%
12 dB
60%
225 MHz
Z0 = 50 
 = 50
400 MHz
225 MHz
400 MHz
41