Transcript 80X86 Instructions - Advanced Microcomputer Systems

8255 I/O
Overview
• 68HC11 pulse accumulator example:
The Egg-O-Matic
• More about the Intel 8255A
• Overview of the Motorola 68HC24
Pulse Accumulator Example: EggO-Matic
• We want a (nearly) perfect 3-minute egg
• Functional concept
o Microcontroller will turn a heating unit on (HEAT = 1)
o Temperature sensor will detect boiling (BOIL = 1 when
boiling)
o Microcontroller will turn heating unit off (HEAT = 0)
• Implementation concept
o Pulse accumulator will be used in “gated-time accumulation
mode”
o Pulse accumulator will count (at E-clock/64) only when boiling
(BOIL = 1)
o An interrupt service routine will execute when pulse
accumulator overflows and will maintain a “big count” to count
for 3 minutes
Cont..
Pulse Accumulator Example: EggO-Matic
Egg-O-Matic initialization (1)
• Pulse accumulator control register (PACTL)
o DDRA7 =1: PA7 (PAI) is input only
o PAEN = 1: Pulse accumulator system enabled
o PAMOD = 1, PAEDGE = 0: Zero on PAI inhibits counting
• Turn on interrupt
o Set PAOVI bit in TMSK2
• Turn on heat by setting PB0
CONTROL:
PAOV:
NPAOV:
HEATON:
EQU
EQU
EQU
EQU
%01100000
%00100000
%11011111
%00000001
;
;
;
;
PA control value
PA overflow mask (TFLAG2/TMSK2)
Inverted PAOV mask
Heat on mask (in PORTB)
Egg-O-Matic initialization (2)
• Time values
o Pulse accumulator will increment every 64 E-clock periods, i.e.
every 64´(500 ns) = 32 ms for a 2 MHz E Clock
o 250 increments gives 250´(32 ms) = 8 ms of time
o 22,500 overflows of 8 ms each gives 22500´(8 ms) = 180 s = 3
minutes
• Needed:
o Preload PACNT to 256-250 = 6
o Maintain a 16-bit down-counter in software, preload to 22,500
COUNT1: EQU !6
; 250 gives 8 ms with 2MHz E clock
COUNT2: EQU !22500 ; 22500*8ms = 3 mins
Egg-O-Matic: COOKEGG
Subroutine
; Subroutine to start cooking
COOKEGG: LDD #COUNT2
STD BIGCNTR
CLR DONEFLAG
LDAA #CONTROL
STAA PACTL,X
BCLR TFLG2,X,NPAOV
LDAA #COUNT1
STAA PACNT,X
BSET TMSK2,X,PAOV
CLI
BSET PORTB,X,HEATON
RTS
the egg
; Initialize big counter
; Clear done flag (not done)
; Set PA control register
; Clear flag if set
; Preload pulse accumulator
; Enable interrupt
; Turn heater on
; Continue with main program
Egg-O-Matic: PA_ISR
interrupt service routine
PA_ISR:
EXIT:
LDX #REGBASE
LDAA #COUNT1
STAA PACNT,X
BCLR PACTL,X,PAOV
DEC BIGCNTR
BNE EXIT
BCLR PORTB,X,HEATON
BCLR TMSK2,X,PAOV
COM DONEFLAG
RTI
; Register base address
; Reload pulse accumulator
;
;
;
;
;
;
;
Clear overflow flag
Decrement big count
Exit if not done
Done. Turn off heat
Turn off interrupt
Mark as done
Return from interrupt
8255 Programmable Peripheral
Interface (PPI)
• Different peripheral chips may be added to an
expanded mode 68HC11
• Consider the 8255A Programmable Peripheral
Interface (PPI)
o Intel peripheral family - 8085, MCS-51, 80x86
o Provides a set of programmable (parallel) I/O ports for use in a
wide range of microprocessor systems and applications
o 24 programmable I/O pins
 8-bit port A
 8-bit port B
 8-bit port C, split into two 4-bit halves
o Three modes of operation
 Basic input or output (mode 0)
Cont..
8255 Programmable Peripheral
Interface (PPI)
 Strobed input or output (mode 1)
 Bidirectional input-output (mode 2)
o Direct bit set/reset (port C)
o Packaged in a 40-pin DIP
8255A Block Diagram
8255A Pins
• Processor interface
o
o
o
o
o
D7-D0: Data bus to/from microprocessor
CS’: Chip select (active low)
RD’: Read enable (active low)
WR’: Write enable (active low)
A1, A0: Register address bits
 00 = Port A
 01 = Port B
 10 = Port C
 11 = Control Register (write only)
o RESET: Chip reset
Cont..
8255A Pins
• Ports
o PA7-PA0
o PB7-PB0
o PC7-PC0
• Power (VCC) and ground (GND)
8255A Modes
• Mode 0
o Simple input or output (unidirectional) operations
o Ports A, B, and C can be programmed to be in Mode 0
 Ports A and B programmed as all 8 bits
 Port C split into high and low nibbles
o Outputs are latched, inputs are not
• Mode 1
o Strobed input or output (handshaking)
o Ports A and B can be used in Mode 1
o Pins from Port C are “borrowed” for handshaking control
signals
 3 bits for Port A , 3 bits for Port B
Cont..
8255A Modes
 Control signals are “data ready,” “data receipt
acknowledge,” “interrupt”
• Mode 2
o 8-bit bidirectional input/output with handshaking
o Only Port A can be used in Mode 2
o Five Port C pins are used for the handshaking and interrupt
request lines
o Port B can be concurrently operated in Modes 0 or 1 (with use
of PC0-2)
8255A control word
• Ports are configured by writing a byte to the Control
Register
o Bit 7 = 1 to select configuration operation
8255A Port C Set/Reset
• Individual bits in Port C can also be set (to 1) or
reset (to 0)
o Control word value indicates bit position and set or reset
o Bit 7 = 0 to select set/reset operation
8255A Mode 0 example:
Hardware
• 8255 is memory mapped at $7F00-$7F03 ($7F00$7FFF used)
• Port A is input, Port C (low) is output
8255 Mode 0 example:
Initialization
PORTA:
PORTB:
PORTC:
CONTROL:
INIT0:
EQU $7F00
EQU $7F01
EQU $7F02
EQU $7F03
LDAA #$90
STAA CONTROL
RTS
; Write control word
; Done
8255A Mode 0 example:
Set/Reset
• Use the set/reset feature of Port C
; Set Bit
; Input:
Bit location in low 3 bits of ACCA
; Changed: ACCA
SETBIT:
ANDA #$03
; Mask other bits
LSLA
; Put in Bit Select field
ORA #$01
; Set S/R bit
STAA CONTROL ; Write to control register
RTS
; Done
8255A Mode 1 Configuration
8255A Mode 1 Input Timing
8255A Mode 1 Output Timing
8255A Mode 1 Status
• Mode 1 status is available in the Port C register
o Read Port C to read status
o Available only if in Mode 1
• Input configuration: (Fig-1)
• Output configuration: (Fig-2)
8255A Mode 2
• Mode 2 allows bidirectional input/output on Port A
o Handshaking
o Protocol to determine whether 8255A or external peripheral can
drive the shared data lines (PA7-PA0)
• Control signals
o
o
o
o
o
STB’:
IBF:
OBF’:
ACK’:
INTR:
Strobe (input)
Input buffer full (output)
Output buffer full (output)
Acknowledge (input)
Interrupt
8255A Mode 2 Configuration
8255A Mode 2 Timing
8255A Mode 2 Status
• Mode 2 status bits are available by reading Port C
(Figure)
•
Group B bits determined by Port B configuration
68HC24 Port Replacement Unit
(PRU)
• Replaces Port B and Port C I/O functions “lost”
when using expanded mode
o PRU’s register set matches the 68HC11 registers for Port B and
Port C for control, status, and data
o Regular expanded mode bus cycles are used to access the PRU
• Primary application is development systems
o Final design can use on-chip 68HC11 ports and memory
o There are often cheaper ways to implement specific I/O
functions needed for an expanded mode system
• 44-pin PLCC or 40-pin DIP package
Single-chip Mode/Expanded Mode
compatibility
• Addressing
o Port B and Port C register addresses are treated as external
memory by the 68HC11 when it is in expanded mode
o PRU registers are accessed at memory addresses defined for
replaced onchip registers
o PRU supports register address space re-mapping like the
68HC11
• Interrupts
o IRQ’ interrupt line is asserted by PRU for Port B and C interrup
ts
o IRQ’ uses the same vector as the handshake and strobed I/O
interrupts
• There are some subtle (minor) timing differences
o Internal clock signals are not available in the PRU
o STRB signals occur slightly later
PRU Interfacing