Transcript Nessun titolo diapositiva

Advanced Mobile Satellite Systems & Technologies presentation days
ESA/ESTEC – 14-15 November 2000
The ESA MUSIC Project
Design of DSP HW and Analog TX/RX ends
Presentation Outline
• The PROTEO Signal Processing Board
• The MUSIC TX/RX Analog Signal
Conditioning Units
AMSST Presentation Days – 14-15 November 2000
The PROTEO Signal Processing Board
DIG.INP. CON 24
CON 8
EXT. BOARD PROG.
CON 10
EXT. CLK
SIMM xRAM
BIT BLASTER
MEMORY Extension (SRAM or DRAM)
RAM
74LCX245
BUFFERS
LEDLEDLED
AMP. & ADC
IF /
I IN
CON 40
CON
40
ADS807
ADC
CON
40
LEDLEDLED
CON 40
LOGIC
100K Gates CPLD
CON
40
LOGIC
100K Gates CPLD
CON
40
TO LOGIC
ANALYZER
74LCX245
BUFFERS
OPA2681
FLEX
10K100A
CPLD
BUFFERING
Q IN
ADS807
ADC
FLEX
10K100A
CPLD
74LCX245
BUFFERS
OPA2681
ICD2053B
Prog.CLK
AGC1 VC
AD5323
DAC
AD5323
DAC
ANALOG
AGC
ICD2053B
Prog.CLK
TO LOGIC
ANALYZER
CON 40
VCXO
AFC VC
CY7B991
ROBOCLK
DSP + Glue Logic
MASTER CLK GEN.
AGC2 VC
EXT. CLK
RAM
78S
05
78S
05
LM
317T
LM
317T
+12 V
+5 V
ST18952
TL7702 POR
MAX
7032
POWER SUPPLY & P-ON RESET
LED
CON
40
RESET
FLASH
QS3238
BUS SW
JTAG
AMSST Presentation Days – 14-15 November 2000
The PROTEO Signal Processing Board
DIG.INP. CON 24
CON 8
EXT. BOARD PROG.
CON 10
EXT. CLK
SIMM xRAM
BIT BLASTER
MEMORY Extension (SRAM or DRAM)
RAM
74LCX245
BUFFERS
LEDLEDLED
AMP. & ADC
IF /
I IN
CON 40
CON
40
ADS807
ADC
CON
40
LEDLEDLED
CON 40
LOGIC
100K Gates CPLD
CON
40
LOGIC
100K Gates CPLD
CON
40
TO LOGIC
ANALYZER
74LCX245
BUFFERS
OPA2681
FLEX
10K100A
CPLD
BUFFERING
Q IN
ADS807
ADC
FLEX
10K100A
CPLD
74LCX245
BUFFERS
OPA2681
ICD2053B
Prog.CLK
AGC1 VC
AD5323
DAC
AD5323
DAC
ANALOG
AGC
VCXO
AFC VC
ICD2053B
Prog.CLK
TO LOGIC
ANALYZER
CON 40
CY7B991
ROBOCLK
DSP + Glue Logic
MASTER CLK GEN.
AGC2 VC
EXT. CLK
RAM
78S
05
78S
05
LM
317T
LM
317T
+12 V
+5 V
ST18952
TL7702 POR
MAX
7032
POWER SUPPLY & P-ON RESET
LED
CON
40
RESET
FLASH
QS3238
BUS SW
JTAG
AMSST Presentation Days – 14-15 November 2000
PROTEO Functional Block Diagram
IF Dig. In
from PC/WS
I
Byte
Blaster
ext.
CLK2
Ext. Board Prog.
5
+
Enable
SRAM Mem.
256Kx16
Buffer
CPLD
Config.
DATA
Ext. Memory Module
(optional)
CY7C1041V33
74LCX245
IF /
I in
I
Amp.
OPA2681
Q in
I
12bit
ADC
2Vpp
12
ADS807
Amp.
2Vpp
5
12
Buffer
CPLD
Flex
10K100A
74LCX245
12bit
ADC
12
ADS807
Buffer
Fout=Fo4*(M/N)
Glob.
CLK1
Glob.
CLK2
74LCX245
Fout=
Fo3*(M/N)
Fs
4
O
A
Dual
B
DAC
AD5323
Dual
AFC
B
option
DAC
A
ext.
CLK1
VCC VDD CPLD DSP
3V3
3V3
5V
5V
16
Bus
Switch
YBus
8
Fo1
FRef
Fo2
32
8
ICD2053B
AD5323
Vz
Vcxo
Prog.
Clock
ICD2053B
Glob.
CLK1
Glob.
CLK2
CPLD
Flex
10K100A
3
3
Prog.
Clock
4
AGC1
AGC2
36
12
Data/Cntrl
OPA2681
72
38
12
8
QS3R384
Interrupts
& Flash Mng.
MAX7032
Fo3
Clock Gen.
&
Skew Mng.
CY7B991
Set Pull Up/Down Resistors
Fo4
IBus
Fo5
Xtal
27MHz
16bit
DSP
ST18952
16
STM29W800
XBus
16
RESET
Voltage Reg.
SRAM
D Mem.
64Kx16
CY7C1021V
TL7702
P-on
Reset
FLASH
P Mem.
4Mx16
JTAG
IEEE 1149.1
AMSST Presentation Days – 14-15 November 2000
I/O
to/from
Ext.
Board
O
State
Anal.
/ other
PROTEO Board Main Features Summary
•
•
•
•
•
•
•
12 bit pipelined ADC Converter (BB ADS807) up to 53MHz sampling.
100 Kgates CPLD (Altera Flex EPF10K100A):
- clock >100MHz;
- usable gates: 90%;
- embedded array blocks: 12 (ex. RAM, ROM, FIFO functions);
- in-circuit re-configurability via Byte-Blaster or JTAG port.
66 MIPS 16bit DSP (ST18952).
On board Memories:
- x CPLD: SRAM 256Kx16 & SIMM-like Module for SRAM 1MB or SDRAM
4MB;
- x DSP : SRAM 64Kx16, FLASH 4Mx16.
Master Clock distribution by Prog. Skew Clock Buffer (Cypress CY7B991):
- selectable skew to 18ns (+-12 time units of 1.5ns).
Prog. Clock Generator (Cypress ICD2053B) for CPLD only:
- clock out : 391KHz-90MHz;
- prog. "on the fly" by 2 wire serial interface.
2x 12 bit dual DAC converters (Analog Device AD5323) :
- high-speed serial interface control logic (up to 30 MHz).
AMSST Presentation Days – 14-15 November 2000
PROTEO Clocks Distribution
DIG.INP. CON 24
CON 8
EXT. BOARD PROG.
CON 10
EXT. CLK2
SIMM xRAM
BIT BLASTER
CON
40
RAM
74LCX245
BUFFERS
IF /
I IN
CON 40
CON
40
CON
40
CON
40
ADS807
ADC
LED LED LED
LED LED LED
CON 40
TO LOGIC
ANALYZER
74LCX245
BUFFERS
OPA2681
FLEX
10K100A
CPLD
Fo * M/N
Q IN
ADS807
ADC
ICD2053B
Prog.CLK
(1)
AGC1 VC
AD5323
DAC
Fo = 16.384 MHz
AD5323
DAC
AFC VC
FLEX
10K100A
CPLD
CON
40
(4)
(3)
74LCX245
BUFFERS
OPA2681
Fo * M/N
VCXO
Fo
ICD2053B
Prog.CLK
TO LOGIC
ANALYZER
CON 40
CY7B991
ROBOCLK
Fxtal 27MHz
(5)
AGC2 VC
(2)
EXT. CLK1
RAM
78S
05
LED
+12 V
78S
05
LM
317T
LM
317T
+5 V
ST18952
DSP
FLASH
Note :
-6 tu, +6 tu, :2, :4 (1,2)
-6 tu, +6 tu, :2, Neg (3)
TL7702 POR
RESET
MAX
7032
QS3238
BUS SW
JTAG
AMSST Presentation Days – 14-15 November 2000
-4 tu, +4 tu (4)
-4 tu, +4 tu (5)
tu = 1.4 ns
MUSIC Breadboard System Overview
MAIN "PROGRAMMABLE" BOARD
TX TEST SIGNAL
GENERATION &
RX ANALOG F-E
EXTENSION BOARD
CPLD
CPLD
DSP
AMSST Presentation Days – 14-15 November 2000
EC-BAID
MUSIC TX - System requirements
•
•
•
•
•
IF Carrier Frequency:
Max Carrier Frequency Uncertainty:
TX Output Power Level:
Spurious and Harmonics:
In-Band Ripple:
70MHz
+/-100 Hz
-10 to -30 dBm
<40 dBc
<0.1 dB
AMSST Presentation Days – 14-15 November 2000
The MUSIC TX/RX: Analog IF Front End
Control
via IEEE488
Mixer
TP
fIFD
TestPoint
fIF
AWG
Download
via IEEE488
Arbitrary
Waveform
Generator
NOISE
GENERATOR
Signal
+MAI
Low-pass
Filter
fLO
TP
B-P
Filter 1
Signal
+MAI
+Noise
T
L.O.
Ext.in
TX SECTION
PLL
L.O.
TP
to
MUSIC Receiver
Digital Section
fIF
TP
IF
IF 70MHz
1V p-p
Diff.out
VGA
BALUN
IF N
B-P
Filter 2
TP
Vagc
RX SECTION
AGC
AMSST Presentation Days – 14-15 November 2000
Up-conversion TX board Block Diagram
Active Mixer: Analog Device AD831
LO Drive required (min): -10 dBm
P1dB:
+10 dBm
IP3:
+24 dBm
Control
via IEEE488
Mixer
fIF
fIFD
AWG
Download
via IEEE488
NOISE
GENERATOR
Signal
Arbitrary
Waveform
Generator
+MAI
Low-pass
fLO
Filter 1
Filter
T
L.O.
Ext.in
LC Butterworth Low-pass Filter
B-P
TestPoint
TX SECTION
Signal
+MAI
+Noise
LO 65.536 MHz
Order:
5
3-dB Bandwidth: 7.5 MHz
TCXO
TCXO: Fordahl DFA 36-MS
Nom Frequency:
65.536 MHz
Output Load:
Sine 0 dBm (50 Ohm)
Frequency stability: +/- 1 ppm
SAW Filter: SAWTEK 854657
1-dB Bandwidth: 3.25 MHz
Insertion Loss: 7.7 dB
In-band ripple: 0.8-1 dB
Group delay in spec
AMSST Presentation Days – 14-15 November 2000
P1dB Measurements
•P1dB (input): +10 dBm
Compression Gain
Output Power [dBm]
10
0
-10
-20
-30
-40
-50
-60
-50
-40
-30
-20
-10
0
Input Power [dBm]
AMSST Presentation Days – 14-15 November 2000
10
20
Harmonics and in-band ripple
•Max Outband spurious level:
-44 dBc
•Isolation LO to Output:
-65 dB
•In-band ripple (Pin=0dBm):
1 dB
-8
-8.5
-9
-9.5
-10
-10.5
-11
-11.5
-12
-12.5
-13
68.7
68.9
69.1
69.3
69.5
69.7
69.9
70.1
70.3
70.5
70.7
AMSST Presentation Days – 14-15 November 2000
70.9
71.1
71.3
MUSIC RX AGC board Block Diagram
Op-Amp: TL082
to
MUSIC Receiver
Digital Section
IF 70MHz
1V p-p
Diff.out
IF N
VGA 2
TP
VGA 1
BALUN
fIF
Signal
+MAI
+Noise
B-P
Filter 2
RX SECTION
VGA: Philips SA5219
Amp2
Amp1
TP
Bandwidth: 700 MHz
7 dB Noise Figure Min
0-1V gain control pin
error signal
BUFFER
LOG AMP RSSI
Low-Pass
filter
SAW Filter: SAWTEK 854657
-
1-dB Bandwidth: 3.25 MHz
Insertion Loss: 7.7 dB
In-band ripple: 0.8-1 dB
Group delay in spec
+
Vref
Op-Amp: TSH31
RSSI: Analog Devices AD8307
1 pole RC filter
Dynamic range:
92 dB
Slope:
25 mV/dB
AMSST Presentation Days – 14-15 November 2000
Control loop
to
MUSIC Receiver
Digital Section
IF 70MHz
1V p-p
Diff.out
IF N
VGA 2
TP
VGA 1
BALUN
fIF
Signal
+MAI
+Noise
B-P
Filter 2
RX SECTION
Amp2
Amp1
TP
BUFFER
LOG AMP RSSI
-
Low-Pass
filter
+
Vref
Loop stability!!
Loop gain
Loop Bandwidth
AMSST Presentation Days – 14-15 November 2000
Loop error
Loop Bandwidth
•Loop Bandwidth must be limited in order to
avoid input signal modulation.
•Loop bandwidth fixed:
200 Hz
•Loop gain:
~20 dB
AMSST Presentation Days – 14-15 November 2000
HP-ADS Simulation Schematic
AMSST Presentation Days – 14-15 November 2000
HP-ADS Simulation Input Signal
•Input Signal Average Power Dynamics:
•Average Fading rate:
20 dB
20dB/3ms
AMSST Presentation Days – 14-15 November 2000
HP-ADS Simulation Results
•20 dB Input Power
Dynamics
•1 dB Output Power
Dynamics
AMSST Presentation Days – 14-15 November 2000
Conclusions
• Implementation of TX and RX boards
• Testing and measurements has confirmed
simulations results
AMSST Presentation Days – 14-15 November 2000