Transcript DisplayPort Link Layer Webinar.

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Quantum Data DisplayPort Link Layer Test Solutions
using the 882EA Test Instrument
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QUANTUM DATA
OVERVIEW
Mission Statement
Quantum Data invents test instruments that help manufacturers bring nextgeneration audio, video, and control products to market – faster and without
interoperability problems.
History
Headquartered in Elgin, IL, Quantum Data has been at the leading edge of
programmable video test generator technology for nearly 30 years.
Quantum Data was founded in 1979 by Allen and Ann Jorgensen and has
been at the leading edge of programmable video test generator technology
since its inception. Over the years, the company has expanded the scope of
its products to include other types of video test equipment.
Global Presence
Quantum Data has distributorships and service centers throughout the
world including: European Union, China, Taiwan, Japan, Korea, Singapore,
Malaysia, Latin America, etc.
You’ll find Quantum Data instruments in the Authorized Test Centers and
design laboratories and production facilities of major consumer electronics
and information technology manufacturer’s throughout the world.
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SOLUTIONS
QUANTUM DATA DISPLAYPORT LINK LAYER
TEST SOLUTIONS
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Activation
keys
SOLUTIONS
882EA front
panel
882EA TEST
INSTRUMENT
882EA - Front
Aux channel port
(connects to source)
Aux channel port
(connects to sink)
DisplayPort
receive port
DisplayPort
transmit port.
882EA - Rear
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SOLUTIONS
882EA TEST
SOFTWARE
• 882EA Link layer compliance test (VESA APPROVED!)
– Applications
• Tests link layer compliance on source devices under test.
• Tests link layer compliance on sink devices under test.
– Operation
• Can be run link layer compliance test through front panel
• Can be run link layer compliance test through GUI application.
• Can be run link layer compliance test through command line.
• 882EA Auxiliary Channel Analyzer
– Applications – monitors aux channel transactions including link
transactions.
• Monitor link training during link layer compliance testing.
• Monitors link training or link maintenance transactions during normal operation.
– Configurations
• Monitors link transactions between 882EA and source devices under test.
• Monitors link transactions between 882EA and sink devices under test.
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LINK LAYER
LINK LAYER OPERATION
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LINK LAYER
TESTING
APPROACH
• What approach can developers of DisplayPort products take to
ensure robust link layer solutions?
– Ensure products are compliant.
– Ensure product are interoperable.
• Compliance first – then interoperability.
– Compliant products may not interoperate together.
– Noncompliant products may still interoperate.
• What tools are available for developers of DisplayPort products?
– Link layer compliance test tools.
– Link layer monitoring tools.
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INFORMATION
DISPLAYPORT LINK
LAYER FUNCTIONS
• Link Initialization (“link training”)
– Link training must be performed unless the Source Main Link transmitter
and the Sink Main Link receiver are already in synchronization.
– Link training follows hot plug – Transmitter (source) device detects a
HPD low-going pulse that exceeds 2ms in width.
• Link Maintenance
– Source must check Link Status when it detects possible main link
synchronization loss (IRQ HPD from sink with low pulse between 0.5ms –
1ms).
– Must link train upon synchronization loss.
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OVERVIEW
DISPLAYPORT LINK
TRAINING
PROCESS
• Link training follows hot plug - source device detects a HPD lowgoing pulse that exceeds 2ms in width.
• Two phases in link training:
– Clock Recovery - locks the receiver CR (clock recovery) PLL to the
repetition of D10.2 data symbols.
– Channel Equalization – achieves symbol lock and inter-lane alignment:
• Symbol Lock - Receiver (Sink) has properly detected and aligned the
ANSI8B/10B symbol boundaries.
• Inter-lane alignment – Sink has successfully aligned the symbol boundaries of
all lanes with one another.
– Must complete in 10ms.
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
Physical connection
for testing a
DisplayPort sink
device.
READ SINK DPCD
CAPABILITIES
Sink supports link
rate of 2.7Gb/s
and 4 lanes.
Source reads sink
DCPD link
capability register
001h.
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
Source writes to sink
DCPD link configuration
register 100h to set link
training parameters
WRITE LINK
PARAMETERS TO
SINK DPCD
Source writes link
rate of 2.7Gb/s and
4 lanes
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
Source writes to
sink DCPD link
configuration
register 102h to set
Training Pattern
BEGIN CLOCK
RECOVERY
Set main link to
send Training
Pattern 1 for Clock
Recovery
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
Source writes to
sink DCPD link
configuration
register 102h to set
Training parameters
SET DPCD LINK
CONFIGURATION
Settings used for
link training
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
CHECK CLOCK
RECOVERY DONE
Source reads sink
DCPD link status
register 202h to check
on link status
Clock recovery is
Done (Set)
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
BEGIN CHANNEL
EQUALIZATION
Source writes to sink
DCPD link configuration
register 102h to begin
Channel Equalization
Training pattern
set to 2
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
CHECK CHANNEL
EQUALIZATION
DONE
Source reads sink DCPD
link status register 202h
to check on Channel
Equalization
Channel Equalization
and Symbol Lock
Done (Set)
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LINK LAYER
LINK TRAINING
NORMAL
OPERATION
WITH SINK
CHECK LINK
TRAINING DONE
Source reads sink DCPD
link status register 202h
to check on Link Training
completion
Training not in progress –
Link training done
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LINK LAYER
ANALYSIS
LINK LAYER ANALYSIS
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Physical connections for
passive monitoring.
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PHYSICAL SETUP
PASSIVE
MONITORING FOR
ANALYSIS
BETWEEN SOURCE
AND SINK DEVICES
Connect the source
device to the ACA port
labeled To Source.
Connect the sink device
to the ACA port labeled
To Sink.
DisplayPort
Sink device
DisplayPort
Source device
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LINK LAYER
ANALYSIS
TEST CASE #1
Sample test case for
passive monitoring.
SOURCE BEGINS
LINK TRAINING
WITH VOLTAGE
SWING OF 1
Source begins Link
Training with voltage
swing level of 1 rather
than 0.
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LINK LAYER
ANALYSIS
TEST CASE #2
Source writes to sink
DCPD link configuration
register 102h to set Link
Training pattern.
Second sample test case
for passive monitoring.
LINK TRAINING
SHIFTS TO LOWER
LANE RATE
Link training
pattern set to 1.
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LINK LAYER
ANALYSIS
TEST CASE #2
LINK TRAINING
SHIFTS TO LOWER
LANE RATE
Source reads sink DCPD
link status register 202h
to check Link Training
progress.
Clock Recovery and
Channel Equalization not
set (not completed).
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LINK LAYER
ANALYSIS
TEST CASE #2
Source reads sink DCPD
link status register 202h
to check for change
request in Link Training
parameters.
LINK TRAINING
SHIFTS TO LOWER
LANE RATE
Sink requests preemphasis for link
training.
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LINK LAYER
ANALYSIS
TEST CASE #2
LINK TRAINING
SHIFTS TO LOWER
LANE RATE
Source writes to sink
DCPD link configuration
register 102h to set new
Link Training
parameters.
New link training
parameters – Max
drive current
setting is reached.
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LINK LAYER
ANALYSIS
TEST CASE #2
LINK TRAINING
SHIFTS TO LOWER
LANE RATE
Source writes to sink
DCPD link configuration
register 100h to set new
Link Training lane rate.
Lane rate
reduced to
1.62Gb/s.
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LINK LAYER
ANALYSIS
TEST CASE #3
LINK TRAINING
REQUIRES
LONGER THAN
10MS
Third sample test case for
passive monitoring.
Link Training begins
Link Training
completes >10ms
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LINK LAYER
COMPLIANCE TEST
RUNNING THE LINK LAYER COMPLIANCE TEST
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LINK LAYER
COMPLIANCE TEST
PHYSICAL SETUP
OVERVIEW
First: Make the
physical
connections.
Second: Configure the
capabilities of the device under
test through the LLC GUI, front
panel or command line.
Third: Select the tests you want
to run and then initiate them
either through the GUI, front
panel or command line.
Fourth: You can monitor the link
transactions during the test.
Fifth: When the test is done, you
get a summary and detailed
report.
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LINK LAYER
COMPLIANCE TEST
Connect the source
device to the ACA port
labeled To Source.
Physical test configuration for
running a link layer compliance
test on a source device with
monitoring by the ACA.
PHYSICAL SETUP
SOURCE TESTING
Loop the ACA port
labeled To Sink to the
882EA Rx port.
DisplayPort
Source
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LINK LAYER
COMPLIANCE TEST
Connect the sink device
to the ACA port labeled
To Sink.
Physical test configuration for
running a link layer compliance
test on a sink device with
monitoring by the ACA.
RUN
Connect the ACA port
labeled To Source to the
882EA Tx port.
PHYSICAL SETUP
SINK TESTING
DisplayPort Sink
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RUN LINK LAYER
COMPLIANCE TEST
RUN THE LINK LAYER COMPLIANCE TEST
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REPORT CMD/CNTRL
You can load and existing
configuration from a file on the
882EA or you can load an
existing configuration.
RUN LINK LAYER
COMPLIANCE TEST
SINK
CONFIGURATION
RUN
This tab enables you to
configure the
capabilities of the
device under test.
Configures the test with
the number of lanes that
the sink device under
Configures the test with
test supports.
the masimum lane rate
that the sink device
under test supports.
Configures the test with
the color and sampling
rate supported by the
sink device under test.
Configures whether the
sink device under test
supports test
automation.
Provisions the test with
the DPCD capabilities
registers.
Configures the test with
the formats that the sink
device under test
supports.
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RUN LINK LAYER
COMPLIANCE TEST
SINK TEST
Defines the amount of
time between each test.
This tab allows you to
select the tests you want
to run and to initiate the
test.
These spin boxes
determine how many
times each test is run.
Here is a list of the tests.
You can select which
ever tests you want to
run.
The status of each
test that is run.
You initiate the test here.
You can run the selected
tests multiple times.
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You can load and existing
configuration from a file on the
882EA or you can load an
existing configuration.
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RUN LINK LAYER
COMPLIANCE TEST
SOURCE
CONFIGURATION
RUN
This tab enables you
to configure the
capabilities of the
Configures
the test with
source
device under
the
color
and
sampling
test.
rate supported by the
source
devicethe
under
Configures
testtest.
with
the formats that the
source device under test
supports.
Configures whether the
source device under test
supports test
automation.
Configures the test with
the number of lanes that
the source device under
test supports.
Configures the test with
the masimum lane rate
that the source device
under test supports.
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RUN LINK LAYER
COMPLIANCE TEST
SOURCE TEST
Here is a list of the tests.
You can select which
ever tests you want to
run.
Defines the long hot plug
pulse width supported by
the source device under
test.
This tab allows you to
select the tests you want
to run and to initiate the
test.
These spin boxes
determine how many
times each test is run.
Defines the time
delay between each
test.
The status of each
test that is run.
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LINK LAYER
COMPLIANCE TEST
LINK LAYER COMPLIANCE REPORT
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
HEADER
The Generator
Information section
provides information
about the 882EA
firmware/gateware and
hardware.
The DUT Specific
Information section
provides information
about the capabilities of
the device under test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
DEVICE
CONFIGURATION
Continuation of the DUT
Specific Information
section provides
information about the
capabilities of the device
under test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
DEVICE
CONFIGURATION
Continuation of the DUT
Specific Information
section provides
information about the
capabilities of the device
under test.
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LINK LAYER
COMPLIANCE TEST
REPORT
Test Summary section
provides a Pass/Fail
indication of the test.
SOURCE TEST
Test Details section provides a
details about each distinct
event in the test.
The details section tells you if
each distinct event in the test
passed or failsd. This enabls
you to pin piont the point of
failure of the test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
Typical example of the
details section of a link
layer compliance test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
Another typical example
of the details section of a
link layer compliance test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
Final status in the details
section of a link layer
compliance test.
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LINK LAYER
COMPLIANCE TEST
REPORT
Test Summary section
provides a Pass/Fail
indication of the test.
SINK TEST
Test Details section provides a
details about each distinct
event in the test.
The details section tells you if
each distinct event in the test
passed or failsd. This enabls
you to pin piont the point of
failure of the test.
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LINK LAYER
COMPLIANCE TEST
REPORT
SOURCE TEST
DEVICE
CONFIGURATION
Typical example of the
details section of a link
layer compliance test.
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LINK LAYER
COMMANDS
CONTROL OF THE LINK LAYER
THROUGH COMMANDS AND FRONT PANEL
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LINK LAYER
COMMANDS
• You can directly control the DisplayPort link layer either through the
882EA front panel or the command line.
• Front panel (or virtual front panel) control functions
– Change number of lanes.
– Change lane rate.
– Change any format parameter, e.g. colorimetry, sampling, etc.
• Command line control.
– Read and DPCD register from a DisplayPort sink.
– Write to any writable DPCD register from a DisplayPort sink.
– Change any format parameter, e.g. colorimetry, sampling, etc.
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Front Panel operates the
same as the virtual front
panel shown below.
LINK LAYER
CONTROLS
FRONT PANEL
Sets the number
of lanes.
Enable or disable
scrambling.
Sets the lane
rate.
Initiates link
training.
Forces link
training with the
specified values.
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
These commands control
the DPCD of the sink device
connected to the 882EA.
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SINK TESTING
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LINK LAYER
CONTROL
COMMANDS
SOURCE TESTING
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LINK LAYER
CONTROL
COMMANDS
SOURCE TESTING
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