Transcript ENGG 3640: Microcomputer Interfacing
ENG3640 Microcomputer Interfacing
Week #7 Data Acquisition System, Part (A)
Topics
Data Acquisition Systems Digital-to-Analog Converters Analog-to-Digital Converters MCU12 ADC Signal Conditioning
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Resources
Huang, Chapter 12, Sections
12.1 Data Acquisition Systems 12.2 Basics of A/D Conversion 12.3 The HCS12 A/D Converter 12.6 – 12.8 Sensors
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68HC812A4 Block Diagram
1-KB SRAM
4-KB EEPROM CPU12 Interrupts Port AD Analog to Digital Port T Timer Module I/O Ports I/O Ports ENG3640 Fall 2012 4
Data Acquisition System
The
purpose
of any data acquisition system is to
acquire analog signals
and present them to the MCU in a form that can be manipulated.
1.
The
main components
of any general data acquisition system consists of the following:
Transducers (sensors) 2.
3.
4.
5.
6.
7.
8.
Analog Multiplexer Signal Conditioning (Amplification, Filtering, ..) Sample and Hold Circuit
Analog to Digital Converter
Microcomputer System
Digital to Analog Converter
Actuator
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Data Acquisition Components
Transducers (sensors) convert variable processes such as pressure, temperature into electrical signals such as voltage or current.
1.
2.
3.
Signal conditioning :
Isolation & buffering
: protection from dangerous voltages (i.e. interfacing an MCU to a 110V or 220V)
Amplification
: Need full scale signal for conversion (transducers usually provide very small signals millivolts)
Bandwidth limiting
: Low pass filter to limit range (noise) Sample and Hold : used to keep signals constant while converting an analog signal to digital A/D and D/A world are interfaces to the MCU to the outside Actuators : interfaces to activate motors, switches, e.t.c
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Signal Paths of a DAS
Humidity Temp Real Pressure …… World Measurand Transducer (sensors) Analog Mux Signal Conditioning Actuator D/A Conv MCU A/D Conv ENG3640 Fall 2012 Sample and Hold Circuit 7
Signal Conditioning: Op-Amps
Inverting Non-inverting
Operational Amplifiers are electronic devices used to amplify signals, filters, signal conditioning, e.t.c.
It consists of three terminals (two inputs, one output) OP-AMPs require dc power to operate (+V CC , -V cc )
OPERATION:
OP-AMPS are designed to sense the difference between the voltage signals applied to its two input terminals (V 2 number V 1 )
A
– V 1 ) , multiply this by a , and cause the resulting voltage
A
(V 2 to appear at output terminal 3.
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1.
2.
3.
4.
Operational Amplifiers: Rules for Analysis
+12V +12V Inverting Non-inverting -12V -12V
Voltage ranges are bounded by supply voltage i.e +/- 12V Input currents are zero because input impedance is large (infinite input impedance for ideal op-amp) Positive feedback or no feedback drives output to saturation (i.e. +12V and -12V) A Virtual short circuit exists between the two input terminals (i.e. whatever voltage is at terminal 2 will automatically appear at terminal 1) due to infinite gain A.
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Inverting OPAMP
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Analysis of Inverting OPAMP
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1.
2.
3.
4.
Inverting Adder
According to virtual ground rule, voltage at inverting and non-inverting inputs are 0.
According to Ohm’s law: i 1 = V 1 /R 1 , i 2 = V 2 /R 2 , … All these currents sum together to produce the current i; that is i = i 1 + i 2 + i 3 (will be forced to flow through R f ) The output voltage V 0 = 0 – iR f = -iR f ENG3640 Fall 2012 12
Binary Weighted DAC
1.
2.
3.
The binary weighted DAC is the simplest converter.
This DAC creates currents that are proportional to the weight of each code bit.
The inverting OP AMP can produce an output voltage which is linear combination of several input voltages.
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Binary Weighted DAC
By using input resistors which scale by a factor of 2, a summing Op Amp can produce an output which follows a binary pattern.
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Binary Weighted DAC
By
using switches on the input resistors
, a summing Op Amp can produce an output which is a binary number (representing which switches are closed) times a reference voltage.
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Binary Weighted DAC
CF = - (R F /R 0 )VB is called the
conversion factor quantum interval
.
or The
quantum Interval
is defined as the change in output signal for a unit change of input code, 0000, 0001, 0010 The largest voltage that can be produced by an n-bit binary DAC is V max = (2 n -1)CF NOTE: CF will be set to the maximum allowable value which is limited by the maximum output of the OP-AMP (V OM ) The largest conversion factor is calculated as CF MAX = (V OM )/(2 n -1) ENG3640 Fall 2012 16
Binary Weighted DAC: Example
1.
2.
3.
1.
A 4-bit binary weighted DAC has values of R F R 0 =360K What is the value of R 1 , R 2 , R 3 2.
Calculate = 10K, (a) the conversion factor when VB = -8V (b) and the maximum output of the system.
Solution:
R 0 = 2R So R 1 1 = 4R 2 = 8R 3, = 180K, R 2 = 90K, R 3 = 45K CF = (-R F x VB)/R 0 = -(10)(-8)/360 = 0.222
Maximum output of this system e max = (2 N -1) x CF = 15 x 0.222 = 3.33V
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A-to-D Conversion Samples in the Time Domain
When an analog signal is to be represented by a digital code the range of analog signal is divided into levels (quantization levels) Pulse Code Modulation (PCM) Using level numbers to represent analog signals leads to Inaccuracy
Quantization Error
(shaded region)
Sampling theory states
that if samples are taken of an analog signal, the original analog signal can be recovered if f s > 2B ENG3640 Fall 2012 18
A Simple A/D Converter
I.
II.
III.
IV.
V.
Components: (a) Counter (b) D/A (c) Comparator (d) Latch The counter counts from 0 to 2 n -1 The counter drives the input of the D/A converter The output of the D/A is compared to the input voltage v in When the output of the comparator switches logic this means that the generated voltage of D/A passed the input voltage.
The comparator then latches the counter output to the latch.
Problem with Slope A/D?
it takes 2 n clock cycles for conversion
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Recall: Staircase A/D Converter
Problem with Slope A/D
cycles for conversion it takes 2
n
clock
Can we do better!
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Tracking Converter
Is an improved version of the staircase ADC
If V A increases over previously converted value the counter will count up If V A decreases over previously converted value the counter will count down
Conversion time is Not Constant
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Successive Approximation A/D
Is based on intelligent trial-and-error method
When start signal is asserted the controller instructs the sequencer to Place a `1’ in MSB position of Register.
All other bits remain at `0’ level
A comparator compares two voltage values on its two inputs.
If guess is low then the next MSB is set to `1’ If guess is high then that bit is set to `0’ and the next MSB is set to `1’ Requires N clock periods for N-bit converter.
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Successive-Approximation Example
6-bit A/D with range 0V – 5V Step Size = 5/2
6
= 0.078
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Successive-Approximation Example
4.16 – 4.141 = 0.019
Error is smaller than ½ LSB
Digital output is 110101 ENG3640 Fall 2012 24
Successive Approximation A/D
A Successive Approximation A/D can give the wrong output if the voltage changes during a conversion A Track/Hold or Sample/Hold circuit is needed to hold the input voltage constant during conversion.
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Sample and Hold Circuit
Circuit
Capacitor & Switch It works by charging the capacitor to the input voltage, then disconnecting the capacitor from the input voltage during conversion.
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Concepts and Terminology
Analog signals have a ratio-metric range 1.
2.
3.
These range from a low value to a high value 0V to 5V -2.5V to 12.5V
4mA to 20mA 1.
2.
3.
Binary Code representation for Analog (0V to 5V) 0V $00 5V $FF 2.5V $80 (middle of analog range) • If the analog range starts from a nonzero minimum value it is usually represented by an “offset binary code” e.g. -2.5 V - +12.5V, then -2.5 == $00 ENG3640 Fall 2012 27
Concepts and Terminology
1.
Definitions :Assume an analog signal ranges from 0V-5V, and number of bits used in A/D converter is 3 Offset Minimum Analog Value 0V 2.
3.
4.
Span Max to Min Analog Value Step Size, Quantum Interval 5V-0V = 5V Span/2 n Resolution Refers to the number of bits in ADC and also to smallest analog change corresponding to a change in a bit in the digital number.
5.
6.
Conversion : Analog Number = (
Digital Number
x Step Size) + Offset Digital Number = (
Analog Number
– Offset)/Step Size Dynamic Range (DR) The dynamic range determines the required word size of an ADC. = (Range or Span)/Resolution = 2 n ENG3640 Fall 2012 28
Example
A 6-bit DAC has an analog output range of -2.5 to 5.0V. Calculate the analog output when input is 010101 (i.e. decimal 21) 1.
2.
3.
Solution:
Offset = -2.5
Span = 5 – (-2.5) = 7.5V
Step Size = 7.5V/2 6 = 10/64 = 0.1172V
4.
Analog Output = (digital number x step size) + offset = (21 x 0.1172) – 2.5V = -0.039V
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Example
1.
A temperature sensor has a measurement range of -10 to 140C. The output range is -2.5 to +5mv. It has a resolution of 0.5C.
Determine the # of bits in ADC?
2.
What is the reading of the ADC when the output of the sensor is -1.0 mv?
1.
Solution:
Span = 140 – (-10) = 150 C (or) 5 – (-2.5mv) = 7.5mv
2.
Dynamic Range = 150 C / 0.5C = 300 DR = 300 = 2 n n = log 2 (300) = 8.22 9 bits 1.
2.
Step Size = Span /2 n = 7.5mv/(2 9 ) = 0.01464
Digital Number = (Analog Number – Offset)/Step Size = (-1.0mv – (-2.5mv))/0.01464
= (102) 10 = (001100110) 2 ENG3640 Fall 2012 30
CPU12 ADC Subsystem: Features
1.
Features of the ADC module include: Eight multiplexed input channels 2.
The CPU12 has no DAC!
ADC based on
successive approximation
3.
4.
5.
6.
8-bit Resolution Single or continuous conversion Conversion complete flag with CPU interrupt request.
Selectable ATD clock
CPU12 A/D
The HC12 has a sample/hold amplifier built in.
The Successive Approximation A/D converter has speeds up to several million samples per second.
VRH is the highest voltage the A/D converter can handle VRL is the lowest voltage the A/D converter can handle
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CPU12 A/D
Channel 0
Analog Multiplexer ENG3640 Fall 2012 The HC12 uses an analog multiplexer to allow eight input pins to connect to the A/D converter 33
CPU12 A/D: Control and Status Registers
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CPU12 A/D: Control Registers
ADPU
1: Powers up the A/D ( if ADPU
General Purpose). Stabilization Period!
0, then AD Port SCAN: Perform one conversion or continuous MULT: Conversion of sequential channels or single channel ADPU SCAN MULT
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CPU12 A/D: Channels
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CPU12 A/D: ATDCTL2
Could either use Polling or Interrupt Driven I/O If ASCIE
1, then interrupt requests are enabled.
The ASCIF interrupt FLAG is set = 1, when conversion sequence is complete.
ASCIE ASCIF
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CPU12 A/D: ATDCTL4
Conversion Time = Initial Sample Time + Transfer Time + Final Sample time + Resolution Time SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
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CPU12 A/D: ATDCTL5
The S8CM bit in ATDCTL5 is used to select conversion sequences of either 8 or 4 conversions.
If set to
0, then 4 conversion sequences are selected and remember that the result is stored in ADRH2 and not ADRH6 if CC=1, CB=1, CA =0 (0110) AN6 ADRxH2 S8CM
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CPU12 A/D: Status Registers
1.
2.
SCF (Sequence Complete Flag) In single conversion sequence mode, SCF set at end of conversion In continuous conversion mode, SCF is set at end of first conversion CCF0-CCF7 (Conversion Complete Flags) 1.
2.
Each ATD channel has a CCF flag which is set at the end of the conversion on that channel.
CCF flag can be cleared by reading STATUS REGISTER #1 and then reading the result register of that channel.
SCF
CCF0 CCF7
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CPU12 A/D: LAB
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Using the ATD to Measure Signal
; ------------------------------------------------------------------- ; Main Program ;-------------------------------------------------------------------- ORG $7000 ; 16K on board RAM MAIN: BSR INIT ; branch to init ATC BSR CONVERT ; Branch to conversion DONE: BRA DONE ; Branch to Self ;---------------------------------------------------------------------- ; Subroutine INIT ;---------------------------------------------------------------------- INIT: LDAA #$80 ; Power up ATC STAA ATDCTL2 ; ATD Flags clear normally & Disable Interrupt BSR DELAY ; Delay (100 us) LDAA #$00 ; Select continue conversion in BGND Mode STAA ATDCTL3 ; Ignore FREEZE in ATDCTL3 LDAA #$01 ; Select Final sample time = 2 A/D clocks STAA ATDCTL4 ; Prescaler = Div by 4 RTS
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Using the ATD to Measure Signal
;---------------------------------------------------------------------- ; Subroutine DELAY 100 us ;---------------------------------------------------------------------- ; Delay required for ATD converter to stabilize (100 usec) DELAY: LDAA #$C8 ; Load Acc with “100 usec delay value” DECA ; Decrement ACC BNE DELAY ; Branch if not equal to Zero RTS ; Return from subroutine
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Using the ATD to Measure Signal
; ------------------------------------------------------------------- ; Subroutine Convert ; set-up ATC, make single conversion and store result to a memory location ; Configure and start A/D conversion ; Analog Input Signal: on Port AD6 ; Convert: using single channel, non-continuous ; The result will be located in ADR2H ;-------------------------------------------------------------------- CONVERT LDAA #$06 ; Initialize ATD
SCAN = 0, MULT=0, ; ; S8CM = 0, PAD6, Write clears Flag STAA ATDCTL5 ; 4 Conversions on a Single Conversion ; sequence WTCONV: BRCLR ATDSTATH,#$80,WTCONV; Wait for Sequence Complete Flag LDD ADR2H ; Loads Conversion result (ADR2H) ; into Accumulator RTS ; Return from Subroutine
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Summary
Data acquisition systems consists of several components (i) sensors (ii) signal conditioning, (iii) Analog to Digital Converters, (iv) MCU, (v) Digital to Analog converters.
Engineers must justify the usage of each component in the path and consider (i) Cost, (ii) error Operational Amplifiers are at the heart of Signal conditioning circuits, ADCs, DACs and therefore analysis of these circuits is very important.
Determining the # of bits required by ADC or DAC is important and knowing the sampling frequency is also as important to recover the original signal.
There are several types of ADCs available (next topic) ENG3640 Fall 2012 45
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Example
1.
Given an analog signal with range -5V to +5V and an 8-bit ADC Determine: Offset, Span, Step Size, %Resolution 1.
2.
3.
4.
Solution:
Offset = -5V Span = 5 – (-5) = 10V Step Size = 10V/2 8 = 10/256 = 39.1mv
% Resolution = 0.391% ENG3640 Fall 2012 47