Transcript Slide 1

Final Presentation

Fourth Order Very Fast Voltage Regulator for RF PA

Performed by: Tomer Ben Oz Yuval Bar-Even Guided by: Shahar Porat

Background

Mobile devices such as smartphones, tablet and laptop required to support wireless communication, and yet, to be able to run for a long period of time with out charging.

• One of the most energy consumer in wireless module is the Power Amplifier (PA) that connected to the RF antenna.

• • • Recent trend to reduce the total power of the PA, is by applying Envelope tracking (ET) on the PA supply level. By using this technique, the power of the PA will be change as a results of the required power for transmitting.

In order to apply high efficiency ET, there is a need to use Switching Voltage Regulator (SVR), and not Linear Voltage Regulator (LVR).

In order to reduce frequency switching noise on the PA supply, a 4 th order SVR is being proposed.

Project target

• Develop a 4 th order, high bandwidth Switching Voltage Regulator (SVR), that will be able to supply RF PA, as describe in the figure below.

Project objectives

• Design and stabilize a high efficiency, high BW fourth order voltage regulator.

• Build a good understanding on how each component affects the stability and accuracy for the “real world” implementation of the voltage regulator.

Design Requirements

• Very low power consumption.

• Ripples and overshoot of below 5%.

• SSE of at least 2%.

• Phase margin of at least 35 ° .

• 1 [MHz] envelope tracking bandwidth.

The phases of the project

1. Simple closed loop design 2. Buck converter 3. Adding a compensator 4. Fourth order system 5. Adding Equivalent Series Resistance

Working environment

• Simulink via Matlab • Cadence’s virtuoso.

Simple closed loop design

• Understanding The Principle 𝐴

V out

lim

A

 

V out A A

  1

V in V in

Simple closed loop design

• • • • • Advantages: High Bandwidth Low Overshoot Simple to design • Disadvantage: Power Consumption

Buck converter - Transient

I

max 

I

min  

I

T

V i

V O L

V O

  

V O

Diode

V Diode L T DutyCycle DutyCycle

) )

Buck Converter – Block Diagram Our Buck Simulink implementation

Buck converter - RLC

V out V in

   

sL

RLCs

2

R

Ls

R L

2  4

LCR

2 2

LR C

  1

L C

Buck converter - PWM

A Vc B

DutyCycle

V c

B V O

V DD

DutyCycle

V DD

V c

B V O

V DD

  

c V DD

B V O

V DD A

V c

Buck converter Frequency domain

Buck converter simulation Buck output for given sine wave input

f switching

 10

LC f

sin  1

LC

Buck converter – Linear Model Comparator & Driver Replaced by Constant Gain

Buck converter - Open Loop Bode On the Cross Over point the phase margin is 8

°

So What Is A Compensator

V Out V In

 (1   1  1

f Pole

 0

f Zero

 1  2 

f Zero

 2  2  1 1

R C

2 2

R C

1 1 2 2 )

Compensator – Bode Diagram Locating the Zeroes give the open loop system 90

°

boost

Considerations of choosing the locations of the Zeros

The zeros should give a phase boost of at least 35

°

at the Cross Over.

There is a need to filter the switching frequency and it requires a large attenuation.

Increase in the difference of the zeros can move the Cross Over point 0dB.

Adding The Compensator

Adding The Compensator On the Cross Over point the phase margin is 5

𝟏°

Various Components Values Degrees of freedom in choosing the component values

Fourth order system

 

Zeros Poles

,1   

Poles

,2  1

L C

5 5 1

L C

5 5 1

L C

4 4

Canceling each other Dominant in the TF

Fourth order system – Bode Diagram After adding the 4 th order the system is not stable – Negative phase margin Caused by adding more cross over points

Adding Equivalent Series Resistance The ESR of the inductors add complexity to the Transfer Function but due to their low values one can consider only the damping they apply

ESR Damping Effect As the ESR increases the damping decreases

Final Components Values Name

R1 C1 R2 C2 RL L4 C4 L5 C5

Value 10[MOhm ] 0.159[pF] 0.1[MOhm ] 5.59[pF] 300[m Ohm] 10[nH] 25.4[nF] 1[uH ] 2.56[ uF]

Final System – Step Response Settling time < 1[uS] OverShoot < 2% Working Frequency – 1[MHz] Phase Margin - 53

°

Preparing for Part B

• Achieving a good understanding of the affects of each component to the system for: – Stability – Settling time – Sensitivity

Questions?