Three-Dimensional Microelectronics Integration: Design, Analysis and Characterization Zeynep Dilli

Ph.D. Program Dissertation Proposal

   Introduction & Motivation: 3-D Integration Current trend in electronics: Tighter integration at every integration level:  Device  Gate  Chip  …  Board  Main Board  System Limitations: Speed, compactness, signal clarity, robustness… “Smart Dust” systems   Ideally self-contained, self-powered and small May require mixed-signal integration

…with sidewall connections

 3-D stacking might be the ideal answer

Stacks with cap chips… …with intertier vias

3-D Integration: Advantages & Disadvantages (Compared with 2-D)

1.

2.

3.

4.

5.

6.

7.

8.

• • Net system size reduction Increased active Si area/chip footprint Delay reduction: faster clocks or higher bandwidth Shorter interconnects Lower parasitic & load impedance Potential intra-system noise reduction Potential substrate noise reduction Heterogeneous integration More freedom in geometric design Lower power consumption.

1.

2.

Increased heat-dissipation problems Increased design complexity.

Challenge to the Designer 3-D integration is a subject that ties together chip design, chip physics, device design, circuit design, electromagnetics, and geometrical layout problems.

Outline

 Proof of concept: A 3-D integrated self powering system  Circuit performance in 3-D integration  Passive devices for self-contained 3-D systems

Self-Powered Electronics by 3-D Integration: Proof of Concept

3D system concept: Three tiers    Sensor (Energy harvesting: Photosensor) Storage (Energy: Capacitor) Electronics (Local Oscillator and Output Driver)

i p



Process & Circuit

0.18 μm fully-depleted SOI process    3 metals p-type substrate, ~10 14 Implants: Threshold adjustment,

CBN

source-drain,

PSD

and

NSD

and

CBP

(0.5x10

19 , 1x10 19 ) (5x10 17 ),

Process information

     Silicon islands 50 nm thick Three-metal process Three tiers stacked Through-vias Top two tiers turned upside down

Figure adapted from MIT_LL 3D01 Run Application Notes

Photodiodes: Design Issues



Major problem: The material depth is very small

    Photocurrent=Responsivity [A/W] x Incident Power Responsivity= Quantum efficiency x λ [ μm] /1.24

 For red light, λ [ μm] /1.24 = 0.51

Incident Power = Intensity [W/ μm 2 ] x Area [ μm 2 ]  Sunlight intensity ≈ 1x10 -9 W/ μm 2 Quantum Efficiency: η   = [# electron-hole pairs]/ [# incident photons] Depends on reflectance, how many carrier pairs make it to the outer circuit, and absorption At 633 nm (red light), absorption coef. ≈3.5e-4 1/nm 

amount of photons absorbed in 50 nm depth is (1-exp( αd)) ≈ 0.017

  η = 0.017 x reflectance x ratio of non-recombined pairs ≈ 0.017 x 0.75=0.013

 Photocurrent=0.013 x 0.51 x 1x10 -9 x Area [ μm 2 ] = 6.63 pA/ μm 2

Photodiodes: Design Issues

      Photocurrent=0.013 x 0.51 x 1x10 -9 x Area [ μm 2 ] = 6.63 pA/ μm 2 Photosensitive area: pn-junction depletion region width (W d ) times length Available implants: Body threshold adjustment implants (p-type CBN and n-type CBP, both 5x10 17 cm -3 ); higher-doped source-drain implants and capacitor implants; undoped material is p-type, ~10 14 cm -3 .

Two diode designs: CBN/CBP diode and pin diode (CBP/intrinsic junction)   CBN/CBP diode W d =0.0684 μm; A=0.5472 μm 2 Pin-diode W d ≈ 1.5 μm; A=15 μm 2; possibly problematic To increase: Higher-intensity light; optimal wavelength (higher wavelength increases λ/1.24, but decreases absorption)

Layout Constraints: As many diodes as possible; diodes in regular arrays; need three bonding pads of a certain size; assigned area 250 μm by 250 μm only Layout: 2062 CBN/CBP diodes: 7.48 nA; 52 pin diodes: 5.17 nA



Expect about 12 nA

Photodiodes: CBN/CBP Diode Layout

Photodiodes: pin diode layout

Layout: Tier 3, Diodes and Pads

“VDD” “GND” Oscillator output

Layout: Tier 2, Capacitor

Top plate: Poly Bottom plate: N-type capacitor implant, CAPN Extracted value: 29 pF Expected value: 30 pF

Layout: Tier 1, Local Oscillator

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Circuit Operation

C storage is charged up to a stable level depending on i ph .



Circuit Operation

V rail =270 mV, f osc =1.39 MHz for i ph =15 nA.

3-D System, Further Research, 1

 Test the device once fabrication is completed:  Self-contained system, 250 μm x 250 μm x 700 μm  Design a version to be fabricated at LPS  Greater active photosensor depth  Voltage regulator to prevent diode forward bias current overtaking the photocurrent  Investigate rectifying antennas as alternate power source  Preliminary investigation done on circuit board level  See further work on passive structures

3-D System, Further Research, 2

  Compare yield of 3-D system with planar system of the same footprint area Codify self-powering system design methodology    Photodiode-based:    Photodiode power generation ability: Diode design and chip optical design (microlenses/AR coatings…) Charge storage system: Capacitor, high-k dielectric use Power regulation circuit requirement Rectifying-antenna based:  Antenna properties: Possible low-k dielectric use   Need for a transformer Rectifier diode design Tied to load circuit characteristics

Outline

 Proof of concept: A 3-D integrated self powering system  Circuit performance in 3-D integration  Passive devices for self-contained 3-D systems

3-D Integration: Performance Study

 Speed:  Intra-chip communication  Heat  Generation and dissipation  Noise  Substrate noise  External Interference  Compare performance with planar integrated circuits and connections

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Performance: Speed

Bonding pads, wires: Extra load + parasitics Left: “External” ring oscillator, 11 stages (two stages are shown)

Both are comprised of minimum-size transistors, simulated speed for 31 stages: 132 MHz.

Right: Internal ring oscillator, 31 stages, output to divide-by-64 counter

Internal Osc.

External Osc.

One-stage delay

112 MHz (31 stage) (equivalent to 1.16

GHz for 3 stages) 398 KHz (11 stage) (equivalent to 1.46

MHz for 3 stages) ~330 ps for internal, ~330 ns for external dev.

Speed ratio: 794.5

Load ratio: ~1000

3-D Connections Chip-to-chip communication between different chips with vertical vias that require 12  m x 12  m metal pads Cadence-extracted capacitance for a pad 9.23 fF: Same order of magnitude as inverter load cap

in2 out2 out1 in1

3-D Connections: “Symmetric” Chip

Structures that can be connected in 3D and planar counterparts for comparison

3-D Connections: “Symmetric” Chip

Same 31-stage planar ring oscillator with counter output Also 31-stage 3-D ring oscillator with counter output (On the figure, groups of 5-5-5-5-5-6).

The proper pairs of pads have to be connected to each other through vertical through-chip vias post fabrication for the circle to close. Simulation results: Planar: 142 MHz 3-D, six “layer”s : 122 MHz (six vertical pads as extra load) To counter input

“symmetry” axis

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Performance: Heat

Coupled simulation at device and chip level to characterize chip heating: Generation, distribution and dissipation

Performance: Heat

Modified heat flow equation:

C



T



t

Integrated over a volume to obtain a “KCL” eqn.:

  (

T o

)  2

T



H CV



T



t



f

6   1 

o



T S f



l f

 

V H C th

(

T

Discretized:

l



T l

 1 

t



T l



R i th

 1 2

T l i

 

T l

“C(dV/dt) + (V2-V1)/R =



T l R th

 1 2 ,

k



k



T l R th



T l

 1 2  1 ) 

I l

I”

(

T l

 1

General Algorithm:

Solve device equations for a range of temperatures; set up the chip thermal network including heat generation; assume initial temperatures and solve the thermal network; obtain heat generated by each transistor at that temperature; reevaluate heat generated by each transistor, repeat until convergence )

Also Possible:

Use solver to suggest layout solutions for heat dissipation

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Performance: Heat

Device operation characteristics depend on temperature (e.g. I-V characteristic of a diode) Affects circuit operation (e.g. f osc of a ring oscillator)

Performance: Noise

 Substrate Noise  Modeled as substrate currents [1] or lumped element networks [2]  Characterized with test circuits [3] or S parameter measurements [4] [1] Samavedam et al., 2000 [3] Nagata et al., 2001, Xu et al., 2001 [2] Badaroglu et al., 2004 [4] Bai, 2001

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Performance: Signal Integrity

On-chip interconnects on lossy substrate: capacitively and inductively coupled [1] Characterized with S-parameter measurements Equivalent circuit models found by parameter-fitting [1] Zheng et al, 2000, 2001; Tripathi et al, 1985, 1988…

Performance: Signal Integrity

 Substrate properties and return current paths affect interconnect characteristics  Three modes of operation, affecting loss and dispersion [1]  Mutual inductance from a return current with a complex depth to calculate interconnect p.u.l inductance [2]  Effect of a second substrate stacked in proximity not investigated  Effect of vertical interconnects not investigated [1] Hasegawa et al, 1971 [2] Weisshaar et al, 2002

Performance: Further Research, 1

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Speed:

3-D integrated chip in design revision 

Heating:

Planar heating characterization chip in fabrication; 3-D heating characterization chip being designed 

Noise:

Design a planar chip to model and characterize the substrate noise coupling within; design a 3-D integrated chip to compare noise performances

Performance: Further Research, 2

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Signal Integrity

: Adapting the heat-elements network to coupled interconnect models  Evaluate the sensitivity of different interconnect layouts to external pulses    Set up a coupled network Use random current sources as external pulses to generate a coupling map Design interconnect chips for experimental verification  Interconnect equivalent circuit model/parameter alterations for 3-D integration    Investigate capacitive and inductive coupling to a nearby conductive, electrically disconnected substrate in addition to the associated substrate Derive transmission line parameters Design chips for experimental verification

Outline

 Proof of concept: A 3-D integrated self powering system  Circuit performance in 3-D integration  Passive devices for self-contained 3-D systems

On-Chip Inductors and Transformers

 Self-contained integrated systems may require passive structures:    Communication with other units in the network: on-chip antennas Power harvesting: Rectifying antennas and transformers Various analog circuits-- mixers, tuned amplifiers, VCOs, impedance matching networks: Inductors, transformers, self-resonant LC structures

On-Chip Inductors and Transformers

 Planar inductor design     Number of turns Total length First/last segment length Trace width      Trace separation Metal layer Substrate doping Substrate shields Stacked or coiled structure  Planar inductor modeling  Define an equivalent circuit, parameter-match to measurements  Separate physics based approaches for serial or shunt parameters

De-embedding and Extraction

L Q

  

m

(1/  

m

(1/

Y

11

Y

11 ) ) 

e

(1/

Y

11 ) An on-chip inductor has frequency ranges where it behaves inductively or capacitively: 

----DUT----

 

-----Ref. frame after Open is taken out-------

 

--------Measured reference frame for DUT_full------------

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A Qualitative Look at the Inductance Curve

Different Metal Layers M3: Lowest capacitance, highest Q factor

Planar vs. Stacked Inductors 58072 micron 2 vs. 22500 micron 2

Transformers

Tuning an Inductor with Light

Bottom right:

Shunt capacitance increases; f sr drops ~150-200 MHz

Top right:

Substrate resistance decreases: peak impedance increases

Exploiting Self-Resonance

   Certain circuits need LC tanks  Mixers, tuned LNAs (as a tuned load)  LC filters There is some interest on intentionally integrating inductors with capacitors to obtain an LC tank Use the equivalent circuit model in a circuit design to exploit this effect and investigate optimization; verify experimentally

Passives: Further Research

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3-D inductors in chip stacks

 Investigate multiple-substrate inductor geometries  Electromagnetic modeling, experimental verification  Low-k dielectrics 

Tunable Self-Resonant Structures

 Controlled tuning methodology  Photoelectrical  Electrical  Electromagnetic  Circuit applications

Summary

 3-D Self-contained System Design  3-D System Performance Analysis  Speed  Noise  Signal integrity  Passive Structures for Self-Contained Systems  3-D passives  Tunable passives

…And on another track…

   Engineering education research Helped Direct:  Maryland Governor’s Institute of Technology program, Summer 2001     Co-authored textbook Benjamin Dasher Best Paper Award in FIE 2002 Design of ENEE498D, Advanced Capstone Design  Presented paper in ITHET 2004 Departmental outreach programs  GE program for high school teachers, MERIT students, WIE summer programs Attending PHYS 708: Physics Education Research Seminar   Engineering education is an open research field as well Considering several questions adapted from PER: Student knowledge body characterization; concept lists for EE…