Transcript MicroProgrammed Control

Microprogrammed Control
1
MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
• Nanostorage and Nanoprogram
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Implementation of Control Unit
COMPARISON OF CONTROL UNIT IMPLEMENTATIONS
Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data
Memory
IR
Status F/Fs
Control Unit's State
Timing State
Control
Points
Combinational
Logic Circuits
Ins. Cycle State
CPU
Microprogram
M
e
m
o
r
y
Control Data
IR
Status F/Fs
Next Address
Generation
Logic
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C
S
A
R
Control
Storage
(-program
memory)
C
S
D
R
D
}
C
P
s
CPU
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TERMINOLOGY
Microprogram / Microcode (corresponding to one CPU instruction)
- Consists of microinstructions
- Program stored in memory that generates all control signals required
to execute the instruction set correctly
Microinstruction
- Contains a control word and a sequencing word
Control Word - All control information required for one clock cycle
Sequencing Word - Information needed to decide
the next microinstruction address
Control Memory (Control Storage: CS)
- Storage for microprogram. Generally ROM
Writeable Control Memory (Writeable Control Storage:WCS)
- CS whose contents can be modified
-> microprogram
-> Instruction set
Dynamic Microprogramming
- Computer system whose control unit is implemented with
a microprogram in WCS
- Microprogram can be changed by a system programmer or a user
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TERMINOLOGY
Sequencer (Microprogram Sequencer)
A Microprogram Control Unit that determines the Microinstruction
Address to be executed in the next clock cycle
Sequencing Capabilities Required in a Control Storage
- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
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Sequencing
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Status
bits
Branch
logic
MUX
select
Multiplexers
Subroutine
register
(SBR)
Control address register
(CAR)
Incrementer
Control memory (ROM)
select a status
bit
Branch address
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Microoperations
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Sequencing
CONDITIONAL BRANCH
Conditional Branch
If Condition is true, then Branch (address from
the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.
Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
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Sequencing
MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions
ADD
0000
AND
0001
LDA
0010
STA
0011
BUN
0100
Mapping
Bits
10 xxxx 010
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.
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.
Address
0000
0001
0010
0011
0100
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Storage
Address
10 0000 010
ADD Routine
10 0001 010
AND Routine
10 0010 010
LDA Routine
10 0011 010
STA Routine
10 0100 010
BUN Routine
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Sequencing
MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram
Machine
Instruction
Mapping bits
Microinstruction
address
OP-code
1 0 1 1
Address
0 x x x x 0 0
0 1 0 1 1 0 0
Mapping function implemented by ROM or PLA
OP-code
Mapping memory
(ROM or PLA)
Control address register
Control Memory
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Microprogram
MICROPROGRAM
EXAMPLE
Computer Configuration
MUX
10
0
AR
Address
10
0
Memory
2048 x 16
PC
MUX
6
0
SBR
6
0
15
CAR
Control memory
128 x 20
Control unit
0
DR
Arithmetic
logic and
shift unit
15
0
AC
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Microprogram
MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14
11 10
Opcode
I
0
Address
Sample machine instructions
Symbol
ADD
BRANCH
STORE
EXCHANGE
OP-code
0000
0001
0010
0011
Description
AC  AC + M[EA]
if (AC < 0) then (PC  EA)
M[EA]  AC
AC  M[EA], M[EA]  AC
EA is the effective address
Microinstruction Format
3
F1
3
F2
3
F3
2
CD
2
BR
7
AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
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Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3
F1
000
001
010
011
100
101
110
111
Microoperation
None
AC  AC + DR
AC  0
AC  AC + 1
AC  DR
AR  DR(0-10)
AR  PC
M[AR]  DR
Symbol
NOP
ADD
CLRAC
INCAC
DRTAC
DRTAR
PCTAR
WRITE
F3
000
001
010
011
100
101
110
111
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Microoperation
None
AC  AC  DR
AC  AC’
AC  shl AC
AC  shr AC
PC  PC + 1
PC  AR
Reserved
F2
000
001
010
011
100
101
110
111
Microoperation
None
AC  AC - DR
AC  AC  DR
AC  AC  DR
DR  M[AR]
DR  AC
DR  DR + 1
DR(0-10)  PC
Symbol
NOP
SUB
OR
AND
READ
ACTDR
INCDR
PCTDR
Symbol
NOP
XOR
COM
SHL
SHR
INCPC
ARTPC
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Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD
00
01
10
11
Condition
Always = 1
DR(15)
AC(15)
AC = 0
BR
00
Symbol
JMP
01
CALL
10
11
RET
MAP
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Symbol
U
I
S
Z
Comments
Unconditional branch
Indirect address bit
Sign bit of AC
Zero value in AC
Function
CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
CAR  SBR (Return from subroutine)
CAR(2-5)  DR(11-14), CAR(0,1,6)  0
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Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.
Sample Format
five fields:
Label:
label; micro-ops; CD; BR; AD
may be empty or may specify a symbolic
address terminated with a colon
Micro-ops: consists of one, two, or three symbols
separated by commas
CD:
one of {U, I, S, Z}, where
BR:
one of {JMP, CALL, RET, MAP}
AD:
one of {Symbolic address, NEXT, empty}
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U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
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Microprogram
SYMBOLIC MICROPROGRAM - FETCH ROUTINE
During FETCH, Read an instruction from memory
and decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Symbolic microprogram for the fetch cycle:
FETCH:
ORG 64
PCTAR
READ, INCPC
DRTAR
U JMP NEXT
U JMP NEXT
U MAP
Binary equivalents translated by an assembler
Binary
address
1000000
1000001
1000010
F1
110
000
101
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F2
000
100
000
F3
000
101
000
CD
00
00
00
BR
00
00
11
AD
1000001
1000010
0000000
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Microprogram
SYMBOLIC MICROPROGRAM
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions (as 4 bits in op code field)
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping:
OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Partial Symbolic Microprogram
Label
ADD:
BRANCH:
OVER:
STORE:
EXCHANGE:
FETCH:
INDRCT:
Microops
BR
AD
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 4
NOP
NOP
NOP
ARTPC
S
U
I
U
JMP
JMP
CALL
JMP
OVER
FETCH
INDRCT
FETCH
ORG 8
NOP
ACTDR
WRITE
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 12
NOP
READ
ACTDR, DRTAC
WRITE
I
U
U
U
CALL
JMP
JMP
JMP
INDRCT
NEXT
NEXT
FETCH
ORG 64
PCTAR
READ, INCPC
DRTAR
READ
DRTAR
U
U
U
U
U
JMP
JMP
MAP
JMP
RET
NEXT
NEXT
ORG 0
NOP
READ
ADD
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CD
INDRCT:
when I=1, say, for ADD at 0 address,
and to get Effective Address of data
a branch to INDRCT (a subroutine)
occurs and SBR  return address
( 1 in this case).
RET from subroutine INDRCT
CAR SBR
NEXT
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Microprogram
BINARY MICROPROGRAM
Micro Routine
ADD
BRANCH
STORE
EXCHANGE
Address
Decimal Binary
0
0000000
1
0000001
2
0000010
3
0000011
4
0000100
5
0000101
6
0000110
7
0000111
8
0001000
9
0001001
10
0001010
11
0001011
12
0001100
13
0001101
14
0001110
15
0001111
FETCH
INDRCT
64
65
66
67
68
1000000
1000001
1000010
1000011
1000100
F1
000
000
001
000
000
000
000
000
000
000
111
000
000
001
100
111
Binary Microinstruction
F2
F3
CD
000
000
01
100
000
00
000
000
00
000
000
00
000
000
10
000
000
00
000
000
01
000
110
00
000
000
01
101
000
00
000
000
00
000
000
00
000
000
01
000
000
00
101
000
00
000
000
00
BR
01
00
00
00
00
00
01
00
01
00
00
00
01
00
00
00
AD
1000011
0000010
1000000
1000000
0000110
1000000
1000011
1000000
1000011
0001010
1000000
1000000
1000011
0001110
0001111
1000000
110
000
101
000
101
000
100
000
100
000
00
00
11
00
10
1000001
1000010
0000000
1000100
0000000
000
101
000
000
000
00
00
00
00
00
This microprogram can be implemented using ROM
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Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING MICROOPERATIONAL FIELDS-
microoperation fields
F1
F2
F3
3 x 8 decoder
3 x 8 decoder
3 x 8 decoder
7 6 54 3 21 0
7 6 54 3 21 0
76 54 3 21 0
AND
ADD
Arithmetic
logic and
shift unit
DRTAR
PCTAR
DRTAC
From
From
PC DR(0-10)
Select
Load
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Load
AC
DR
Few functions are shown
as outputs of 3 decoders
Note:
Instead of using gates to
generate control signals
for ADD, AND, and DRTAC
these will become now
outputs of MUX
AC
0
1
Multiplexers
AR
Clock
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Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION
ADDRESS LOGIC
-
Branch, CALL Address
External
(MAP)
S1S0
00
01
10
11
Address Source
CAR + 1, In-Line
SBR RETURN
CS(AD), Branch or CALL
MAP
Address
source
selection
Clock
RETURN form Subroutine
In-Line
3 2 1 0
S1 MUX1
S0
SBR
L
Subroutine
CALL
Incrementer
CAR
Control Storage
MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing  CAR + 1
- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
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Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -
1
From I
CPU S
MUX2
Z
L
Test
BR field
of CS
Select
T
Input
I0 logic
I
1
L(load SBR with PC)
for subroutine Call
S0 for next address
S1 selection
CD Field of CS
Input Logic
I0I1T
000
001
010
011
10x
11x
Meaning Source of Address
In-Line
JMP
In-Line
CALL
RET
MAP
CAR+1
CS(AD)
CAR+1
CS(AD) and SBR <- CAR+1
SBR
DR(11-14)
S1S0
L
00
10
00
10
01
11
0
0
0
1
0
0
S0 = I0
S1 = I0I1 + I0’T
L = I0’I1T
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Design of Control Unit
MICROPROGRAM SEQUENCER
External
(MAP)
L
I
Input
I0
logic
1
T
1
I
S
Z
3 2 1 0
S1 MUX1
S0
SBR
Load
Incrementer
MUX2
Test
Select
Clock
CAR
Control memory
Microops
...
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CD
BR
AD
...
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