1998 Xilinx Corporate Roadmap

Transcript 1998 Xilinx Corporate Roadmap

Design Methodology for High-Density FPGA Design

Selecting an Architecture High-Density Software Methodology Implementation and Integration of Cores

Design Methodology

Channel Interface

System Level FPGA

V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D Spread Spectrum Frequency Channel Allocation Design

Design Methodology

Channel Interface A/D

Challenges of High-Density FPGA Design

Virtex V400 FPGA Transmitter Spectral Analysis PCI CPU and Software Channel Manager

 How to Implement?

 What Architecture ?

 Software Access to Architectural Features?

 Verification Strategy ?

 Use IP Cores ?

Design Methodology

Agenda

 Selecting an architecture — system level FPGA — Smart-IP technology  High-density FPGA software methodology — design flow — — accessing the architecture specific features design verification    Implementation and integration of cores — CORE Generator — — — LogiCORE AllianceCORE design series Software demo Roadmap

Design Methodology

System-Level FPGA

Channel Interface A/D Transmitter Spectral Analysis PCI CPU and Software Channel Manager

 Integrates with software tools?

    High performance I/O standards?

Million system gates?

Performance?

— 100 MHz Memory?

 — SRAM, FIFO IP friendly?

— 133 MHz SDRAM 1 Gbit Ethernet 66 MHz PCI

Design Methodology

Xilinx Smart-IP Technology

 Xilinx Smart-IP Technology — — — architectures tailored to cores intelligent software implementation flexible core technology  Delivers: — — — high predictability high performance high flexibility

Only available from Xilinx Design Methodology

Xilinx Smart-IP Technology

Architecture Tailored to Accept Cores

Xilinx Segmented Routing Non-Segmented Routing Core1 Core2

• • •

Advantages Efficient Routing Predictable Timing Low Power

Design Methodology

Xilinx Smart-IP Technology

Architecture Tailored to Accept Cores

Distributed Memory Local RAM available to the Core

• • •

Advantages Portable RAM-based cores 16x improved logic efficiency High-performance cores

Design Methodology

Xilinx Smart-IP Technology

Pre-defined Placement & Routing

Fixed Placement & Pre-defined Routing Fixed Placement Relative Placement I/Os Guarantees Performance Guarantees I/O & Logic Predictability Other Logic Does Not Affect on the Core Enhances Performance & Predictability

Design Methodology

Xilinx Smart-IP Technology

Delivers Design Predictability

Performance is independent of core placement and number of cores used in the device

80 MHZ 80 MHZ 80 MHZ 80 MHZ

Avoids the performance loss of non-segmented architectures Design Methodology

Xilinx Smart-IP Technology

Delivers Design Predictability

Performance is independent of device size

Avoids the performance loss of non-segmented architectures Design Methodology

Virtex Enables

Channel Interface A/D Virtex V400 FPGA Transmitter Spectral Analysis

System Level FPGA

PCI CPU and Software Channel Manager

 Integrates with software tools?

 High performance I/O standards?

 Million system gates?

 Performance?

— 100 MHz  Memory?

— SRAM, FIFO  IP friendly?

— 133 MHz SDRAM 1 Gbit Ethernet 66 MHz PCI

Design Methodology

Agenda

 Selecting an architecture — system level FPGA — Smart-IP technology  High-density FPGA software methodology — design flow — — accessing the architecture specific features design verification    Implementation and integration of cores — CORE Generator — LogiCORE — AllianceCORE — design series Software demo Roadmap

Design Methodology

The Value of Xilinx Partnerships The most comprehensive “Open System” solution

 Early software support for new devices  New product development maximizing architectural and synthesis capabilities – efficient timing constraints integration – high performance optimization engines tuned for new Xilinx devices – direct optimization & mapping of Carry logic, complex I/O, LUTs, CE, arithmetic operator  Joint definition of next-generation Solutions

Design Methodology

Source Code Design Reuse

AllianceCORE LogiCORE

HDL Editor Schematic Entry

Design Flow

Design Entry Symbol/HDL Sim.Model

Top Level HDL or Schematic

Design Verification Functional Simulation

Synthesis User design only

Timing Simulation Netlist Xilinx FPGA Netlist Constraints

Place & Route

Netlist Static Timing Analysis Design Implementation

Design Methodology

Software Features (ASIC-Like)

 Minimum-delay reporting — hold-time analysis — finds hazards in asynchronous logic — min delay option “-s min” for TRCE and NGDANNO  Voltage and temperature pro rating — can specify a higher voltage than worst case – specify 3.3V instead of 3.0V

— can specify a lower temperature than worst case – specify 55°C instead of 85°C  First SRAM based device to support temp & voltage pro rating and minimum delays

XC4000XL

family supported in A1.5, Virtex to follow

Design Methodology

System Clock FPGA Inst_A

Minimum Delay

System-Level Analysis

Flip-Flop Hold time 1 ns D Q System Clock 1 ns SDRAM

 Internally, Xilinx guarantees 0ns hold times  Identify board-level hold time violations for synchronous designs

System Clock D Q D Q With max tco (for Inst_A) = 5 ns With min tco (for Inst_A) = 2 ns Data not latched

} }

Valid data on Q for worst case delay Hold Time violation for best case delay

Design Methodology

Temperature and Voltage Pro rating

Parameter [ns] Internal Period System Requirements 3.3V, 70 °C 10.0

XLA –08 V = 3.0V

T = 85 °C 10.6

XLA –08 V = 3.3V

T = 70 °C 9.0

XLA –09 V = 3.3V

T = 70 °C 9.4

Clock-to-Out Input Setup 4.0

6.0

4.2

5.8

3.7

5.2

3.9

5.4

 Delays based on worst case process

Meets Requirements

 Adjust temperature and voltage to reflect system operating conditions

Lowest Cost

 Reduce system cost by targeting a slower speed grade

Design Methodology

1 Million Gates In Less Than 5 Hours

Compile Times Gates Per Hour 200k 150k 100k 50k Timing Driven Implementation 35k Gates / hour 50k Gates / hour 200k Gates/ hour

 New place & route algorithms  Abundant & flexible vector based interconnect — 4x routing resource vs XC4000XL — fully populated switch matrix  Buffering of high fanout and long distance interconnects — 8 ns across 250K system gates  Up to 40% smaller interface netlist

0 A 1.5

A 1.4

XC4000XL A 1.5

XC4000XL

Design Methodology

800 700 600 500 400 300 200 100 0

Faster Compiles with Virtex

“

Tough” Customer Designs

Virtex -4 XC4000XL-09 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Suite

Virtex compiles, on average, 28 times faster Design Methodology

200%

Faster Systems with Virtex

“

Tough” Customer Designs

Virtex -4 XC4000XL-09

100% 0

   1 2 3 4 5 6 7 8 9 10 11

Design Suite

12 13 14 15 16 17 18 19 Faster Virtex speeds with silicon characterized speeds files Virtex is faster for 84% of the designs Designs from ATM, PCI, Networking & ISDN applications

Design Methodology

Accessing Technology-Specific Features

 By inference — technology mapping using behavioral constructs that allow code portability — — operators RAM  By instantiation — use gates in the target technology making the code technology specific — — — Block RAM CLKDLL special I/Os.

Design Methodology

Inferring Technology-Specific Features

 Fast arithmetic carry chains  Wide input muxes, “case vs. priority encoder”  RTL flexibility for register configurations  Area-efficient muxes using TBUFs  Distributed RAM inferencing  Registered I/O buffer inference  Timing-driven register IOB mapping

Design Methodology



Fast Arithmetic Functions Using Carry Chains

180 MHz 32-bit arithmetic/counters

Virtex Logic Block Carry

0 1 LUT

if (!reset) count = 32’b0; else count = count + 1’;

 Small 16-bit adders using 16 LUTs — 51 for XC4000XL LUT 0 1 LUT LUT 0 1 0 1

Sum = a_in + b_in

  60MHz 16x16 multipliers — — 30% area reduction compared to XC4000XL 160MHz with pipeline stages Operator Inferencing from synthesis 

mult = a_in * b_in

Pipelined multipliers from the CORE Generator tool

Design Methodology

Priority Encoder “if-then-else”

When to use?

always @(sel or in) begin if (sel == 3'h0) out = in[0]; else if (sel == 3'h1) out = in[1]; else if (sel == 3'h2) out = in[2]; else if (sel == 3'h3) out = in[3]; else if (sel == 3'h4) out = in[4]; else out = in[5]; end in [4] in [3] S in [2] S in [1] S in [0] S

   Assign highest priority to a late arriving critical signal Nested “if-then-else” might increase area and delay Use “case” statement if possible to describe the same function

Design Methodology

Benefits of “Case” Statement

8:1 Mux always @(C or D or E or F or S) begin case (S) 2’b000 : Z = C; 2’b001 : Z = D; 2’b010 : Z = E; 2’b011 : Z = F; 2’b100 : Z = G; 2’b101 : Z = H; 2’b110 : Z = I; default : Z = J; endcase C D E F G H I J Z S

   Compact and delay-optimized implementation — implemented in a single CLB Synthesis maps to MUXF5 and MUXF6 functions 8:1 multiplexor is implemented in a single CLB

Design Methodology

RTL Flexibility for Register Configurations

Positive-Edge Triggered Flip-Flop with clock enable, sync reset and preset preset

always @(posedge clk or posedge preset) begin if (preset) q = 1; else if (reset) q = 0; else if (CE) q = data; end

data ce clk q reset  Register mapping for — — registers with sync/async set and reset clocks, inverted clocks, and clock enable

Design Methodology

Area Efficient Muxes Using TBUFs

case (E) 4’b0001 : Q[7:0] = A[7:0]; 4’b0010 : Q[7:0] = B[7:0]; 4’b0100 : Q[7:0] = C[7:0]; 4’b1000 : Q[7:0] = D[7:0]; endcase A[7:0] B[7:0] C[7:0] D[7:0] Z[7:0] E[3:0] E0 A[7:0] assign Q[7:0] = E0 ? A[7:0] : 8'bzz..z; assign Q[7:0] = E1 ? B[7:0] : 8'bzz..z; assign Q[7:0] = E2 ? C[7:0] : 8'bzz..z; assign Q[7:0] = E3 ? D[7:0] : 8'bzz..z; B[7:0] C[7:0] E1 E2 E3 D[7:0]

  Improve area efficiency by using tri-states Each CLB has 2 TBUFs  Place-and-route can connect tri-states on multiple horizontal Longlines to build wide muxes

Z[7:0]

Design Methodology

Distributed RAM Inferencing System Memory

Synplicity

(RAM 8x4)

RAM 16x1S module ramtest(q, addr, d, we, input we; input clk; clk); output [3:0] q; input [3:0] d; input [2:0] addr; reg [3:0] mem [7:0]; assign q = mem[addr]; always @(posedge clk) begin if(we) mem[addr] = d; end endmodule Addr [2:0] D [3:0] clk we AO A1 A2 A3 D WCLK WE RAM 16x1S AO A1 A2 A3 D WCLK WE Q q [3:0]

 

Synplify

and

Leonardo Spectrum

can infer distributed RAM

FPGA Express

will support RAM inferencing in the future

Design Methodology

Registered I/O Mapping System Interfaces

 System timing — chip-to-chip performance often limits system speeds — registered I/O improves performance  No need to instantiate IOB register cells — implementation tools will pack registers in the IOBs — — map -pr b – b (both input and output) – – i (input only) o (output only) IOB = TRUE attribute  Mapping for data and enable ports

D CE S/R Q CLK D CE S/R Q CLK Q S/R D CE CLK OBUF OBUF IBUF

Design Methodology

Controlling the Inference of Output Registers

process (Tri, Clk) begin if (clk’event and clk =`1`) then Tri_R <= Tri; end if; end process; process (Tri, Data_in) begin if (Tri_R = ‘1’) then Out <= Data_in; else Out <= (others => ‘Z’); end if; end process; TRI D CLK Q TRI_R fanout = 24 DATA [23:0] OUT [23:0]

 Technology mapping will

not

duplicate registers  Critical signal will

not

be absorbed in the IOB register

Design Methodology

Controlling the Inference of Output Registers

process (Tri_, Clk) begin if (clk’event and clk =`1`) then begin else begin Tri_R1 <= Tri; Tri_R2 <= Tri; end if; end process; process (Tri_R1, Data_in) if (Tri_R1 = ‘1’) then Out(23) <= Data_in(23); Out(23) <= ‘Z’); end if; end process; process (Tri_R2, Data_in) if (Tri_R2 = ‘1’) then Out(22:0) <= Data_in(22:0); else Out(22:0) <= (others => ‘Z’); end if; end process; TRI D CLK Q TRI_R1 DATA [23] fanout = 1 OUT [23] TRI D CLK Q TRI_R2 fanout = 23 DATA [22:0] OUT [22:0]

 Duplicates register on critical path for fanout of 1  Mapping will absorb register in IOB

Design Methodology

Instantiating Technology-Specific Features

 Block RAM — system memory  CLKDLL — minimizes clock skew  Special I/Os — interfacing with standard buses  LUTs for datapath pipelining — add latency with minimal area impact

Design Methodology

Block RAM System Memory

component RAMb4_S1 port(WE,EN,RST,CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(11 downto 0); DO: out STD_LOGIC; DI: in STD_LOGIC_VECTOR(0 downto 0)); end component; begin U1: RAMB4_S1 port map(WE=>WE, EN=>EN, RST=>RST, CLK=>CLK, DI=>DI, ADDR=>ADDR, DO=>DO); RAMB4_S1 U1 (.WE(WE), .EN(EN), .RST(RST), .CLK(CLK), .ADDR(ADDR), .DI(DI), .DO(DO)); addr we en rst clk di RAMB4_S1 ADDR WE EN RST CLK D DO do

  Instantiate single- and dual-port RAM Use the CORE Generator to build RAM and FIFO (Q1 ‘99)

Design Methodology

CLKDLL Minimize Clock-to-Out System Timing

   One use of a CLKDLL is to minimize clock to outpad delay — removes all delay from external GCLKPAD pin to the registers and RAM BUFGDLL is available for instantiation Other configurations can be built by instantiating the CLKDLL macro

IBUFG BUFG clkin rst CLKDLL CLKIN CLK0 CLK90 CLK180 CLK270 CLKFB RST CLK2X CLKDV LOCKED U4 clk_fb

Verilog

wire clk_fb; BUFGDLL U4 (.I(clkin), .O(clk_fb));

Design Methodology

Special I/O Buffers

System Interfaces

 Default I/O buffer is LVTTL (12mA), available via inference — process technology leads to mixed voltage systems — high-performance, low-power signal standards emerging  Instantiate I/O buffers for non default current drive — non-default voltage standard — non-default slew 

awire oport OBUF_AGP U0 (.I(awire), .O(oport)); U0

Advanced Graphics Port bus interface (Pentium II graphics app)

OBUF_F_24 U1 (.I(awire), .O(oport));

 Fast slew rate and 24 mA drive strength

awire U1 oport

Design Methodology

LUTs for Datapath Pipelining

 LUT can be used in place of registers to balance pipeline stages — area efficient implementation  SRL16E can delay an input value up to 16 clock cycles  Synchronized operands before the next operation

A[31:0] B[31:0] C[31:0] F G 5 cycles H 7 Z SRL16E

D CE CLK A3 A2 A1 A0 Q

32 LUTs replace 256 registers 8 cycles 1 cycle 12 SRL16E

D CE CLK A3 A2 A1 A0 Q

32 LUTs replace 416 registers

Design Methodology

Design Verification

 Trends  Stages  Xilinx solutions

Design Methodology

What’s Driving the Verification Trends?

Cost of Design Error Over Time

10,000X 1000X $$$ 100X 10X 1X Functional Simulation Synthesis PAR System Test End Product Design Cycle Stages

Functional simulation should eliminate 95% of the bugs

Design Methodology

Stages to Verify the Design

Gate-level Functional Simulation

    Create testbench Verifies syntax & functionality Majority of design cycle time Errors found are inexpensive to fix

Gate-level Functional Simulation

   Checks the synthesis implementation to gates Test initialization states Analyze ‘don’t care’ conditions

Gate-level Timing Simulation

   Post implementation timing simulation Test race conditions Test set-up and holds violations based on operating conditions VHDL or Verilog testbench 4 Synthesis 4 Implementation 4

Design Methodology

What Does Xilinx Provide?

 Libraries and interfaces for simulation throughout the design flow — functional simulation with UNISIM — timing simulation with SIMPRIM  Mixed-mode simulation — schematic and HDL  Minimum-delay analysis  Voltage and temperature prorating  Unique VHDL simulation of global set/reset capabilities

UNISIM Library

Simulation

VHDL or Verilog Synthesis

SIMPRIM Implementation

Design Methodology

Benefits of the Xilinx FPGA Software Development Methodology

 ASIC-like design flow and features — open development system — — minimum delays and temp pro rating robust Verification Flow  Improve designer productivity — faster compile times, better performance  Utilizing device resources — technology independence since most technology features are accessible via inference — use techniques to reduce area and increase performance

Design Methodology

Agenda

 Selecting an architecture — system level FPGA — Smart-IP technology  High-density FPGA software methodology — design flow — accessing the architecture specific features — design verification    Implementation and integration of cores — CORE Generator — — — LogiCORE AllianceCORE design series Software demo Roadmap

Design Methodology

Implementation and Integration of Cores

          PCI PCMCIA HDLC Reed-Solomon MPEG T1 Framer DRAM Controller DMA Viterbi Decoder FIR Filter

A IP B IP C IP

Design Methodology

High-Density FPGA Design Implementation

 Xilinx CORE Generator — reduces time to market — — delivers parameterizable optimized using SmartIP cores technology   LogiCORE products — licensed and supported by Xilinx — highly optimized for Xilinx FPGAs results in best possible performance, area and predictability AllianceCORE products — licensed and supported by Xilinx’ partners — 25 partners provides industry’s widest selection of cores and design expertise  Design services — 3rd party and Xilinx design centers — local expertise and services

Design Methodology

Channel Interface

Xilinx CORE Generator IP Delivery System

Virtex V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D

Design Methodology

Benefits of Using Xilinx Cores

2 Months Design From Scratch Learn Design 9 Months Implement Verify 12 Months Reference Design, Generic Core L D I Complete FPGA Core Solution L D I V V Pre-verified Designs Area & Timing Optimized Complete & Flexible Design Little Knowledge of Function Required

Design Methodology

Benefits of Using Xilinx Cores

“75% of all new designs will have Cores - Designer feedback from IP usage survey in them” “The high performance of the Xilinx PCI LogiCORE solution combined with the short time to market and flexibility of a programmable FPGA solution, made Xilinx the obvious choice." -

Tony Clark, R&D Mgr. - Management Graphics, Inc

“By using ‘Design Reuse’ as part of our design consulting services, on average we are able to save our customers 18 24 weeks” -

Tim Smith of Memec Design Services Design Methodology

CORE Generator Delivery System Xilinx Smart-IP Technology

Parameterized Cores Data sheets CoreLINX: Web Mechanism to Download New Cores SystemLINX: Third-Party System Tools Directly Linked With Core Generator

Free Software & Free Cores Included As Part of The Alliance and Foundation Software Packages Design Methodology

Core Generator Demo

Design Methodology

Channel Interface

Xilinx LogiCORE

Virtex V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D

Design Methodology

Xilinx LogiCORE

 Licensed and supported by Xilinx  Highly optimized for Xilinx FPGAs — module based design flow — best possible performance, area and predictability  Building blocks — can be used as-is, or as foundation for high-level cores — — give users access to architectural features (e.g., LUT and memory) through automatic tools examples: Basic Logic, Arithmetic, Counters, Memories  Standard cores — enable high-performance DSP and PCI applications — use unique implementation techniques to deliver unparalleled performance, area and predictability

Design Methodology

A Complete PCI Solution Enables Cost-Effective Designs

 Widest range of compliant PCI cores — LogiCORE PCI32 (32-bit, 33 MHz cores) — — LogiCORE PCI64 (64/32-bit, 33-66 MHz cores) all support fully compliant 0 wait-state burst  Synthesizable bridge designs — reusable PCI bridge design examples  Hot PCI prototyping board -

Virtual Computer Corp.

 PCI driver development tools and reference drivers -

Vireo Software Inc.

Design Methodology

The Real-PCI™ 64/66 Solution from Xilinx

 Real compliance (PCI v2.2) — — — based on de-facto industry standard PCI FPGA core only FPGA solution with guaranteed timing Compact PCI Hot-Swap friendly  Real flexibility — first 66 MHz PCI core implemented in standard FPGAs  Real performance — full 528 MB/s sustained bandwidth Power by

Design Methodology

PCI32 Spartan - Lowest Cost PCI

$20 $15 $10 External PLD 7K Gates Standard Chip PCI Master I/F * Supported devices: XCS20XL XCS30XL XCS40XL $5 XCS20XL-4 TQ144* 7K Gates Logic

Power by

PCI Master I/F Standard Chip Solution <$7

Design Methodology

Combined Flexibility and Predictability

 Only PCI cores for FPGAs with guaranteed timing — including 2ns clock-to-out min timing, and 0 ns hold — — FPGA characterized together with core pre-defined critical placement and routing  First parameterizable PCI core on the web — instant access to new design files  First core with modular architecture — core de-coupled from back-end design — back-end customizable without affecting PCI timing

Design Methodology

CORE Configuration

Design Flow

Design Entry Symbol Sim.Model

User Design HDL or Schematic Synthesis User design only

CORE Design zip or tar

Netlist Design Verification Functional Simulation Timing Simulation Netlist Constraints Place & Route Netlist Design Implementation

Design Methodology

Accelerate Your DSP Processor

 Performance of a custom IC  Flexibility of a DSP processor — >10 times the performance — — lower cost lower power  Replaces multiple DSP processors  Replaces DSP building block ICs

Implement the cycle intensive algorithms in an FPGA

10 9 8 7 16-bit FIR Filter Benchmark 6 5 4 3 2 1 Highest Performance S40 DSP Processor 4085 Virtex

Design Methodology

Applications

 High performance — data sample rate (> 1MHz) or multiple channels — — alternative to multiple DSP processors alternative to custom ICs  Video, image processing, HDTV, set top boxes — image resizing, enhancement  Data communications, wired & wireless — narrow-band filters, multi-rate filters  Military communications, surveillance, radar, sonar  Data encryption - fast, wide multipliers

Design Methodology

A Complete High-Performance Programmable DSP Solution

 Spartan, XC4000, Virtex  Design tools and DSP IP — LogiCORE & AllianceCORE — — CORE Generator software Elanix - SystemView - integration  DSP prototyping boards  DSP starter kit  DSP support — DSP FAEs, design services

DSP Functions System-Level DSP Modeling Tools

Design Methodology

Channel Interface

Xilinx AllianceCORE

Virtex V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D

Design Methodology

Program

 Partnerships with leading third-party IP providers  Complete programmable logic solutions — proven Xilinx cores — test benches, debug software — hardware evaluation boards  License directly from partner — Xilinx netlist and source code versions — Partner guarantees functionality  Information on the Xilinx web site — www.xilinx.com/products/logicore/alliance/tblpart.htm

Design Methodology

Released Products*

Bus Interfaces CAN FireWire (IEEE 1394) I

C PCMCIA (2 types) USB (3 types) Communications ATM Cell Assembler ATM Cell Delineation 10/100 Ethernet MAC (2) CRC (10- & 32-bit) DES Engine HDLC (2 types) Reed Solomon T1 Framer UTOPIA (master & slave) Viterbi Decoder *As of January, 1999 Image Processing YUV to RGB Processor Peripherals UARTs (7 types) 2910A 8237 8251 8254 8255 (3 types) 8256 8259 (2 types) 8279 9128 DRAM Controller SDRAM Controller RISC Processors (2 types) Demo Boards & Software (15)

Design Methodology

*As of January, 1999

Merged with…

Partners*

Design Methodology

Channel Interface

Xilinx XPERTS Program

ilinx

rogram for

ngineering

esources from

hird partie

S Virtex V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D

Design Methodology

Xilinx XPERTS Program

ilinx

rogram for

ngineering

esources from

hird partie

S  Xilinx certified consultants  Local design services support — ease the targeting of new architectures — PCI, DSP specialists – Accelerate IP design methodology  Cost advantage — Xilinx optimized solution  Partners in all major cities world wide

Design Methodology

Partner Profile

 Specialists in PCI Core customization and integration  DSP specialists — expertise and experience in datacom, telecom, XDSL, networking, video and image processing algorithm designs  Specialists in HDL-based team-based designs and ASIC to FPGA conversions  Details on www.xilinx.com/company/consultants/index.htm

Design Methodology

Benefits of Xilinx FPGA Design Implementation

    Complete programmable logic solutions Xilinx CORE Generator — — — — pre-verified designs complete and flexible design module based design improved time to market LogiCOREs - “Expertise without the effort” — — — Smart IP technology minimum knowledge of function required design optimized for speed and area AllianceCORE IP and XPERTS design services partnerships — — — Leading providers of third-party IP and design services Smart IP technology* world-wide access to expertise *All AllianceCORE modules are optimized for Xilinx

Design Methodology

Channel Interface

Software Demo Putting It All Together

Virtex V400 FPGA Transmitter PCI CPU and Software Channel Manager Spectral Analysis A/D

Design Methodology

Software Design Flow Demo

Design Methodology

Roadmap

 Software  Cores  Web Access and Resources

Design Methodology

Major Software Features 2.1

 Floorplanning — detailed and modular physical layout (manual or from synthesis) — interface to 3rd party RTL floorplanners  Implementation — place-and-route optimized for modular area constraints — — — critical timing path optimization within modules much faster runtime for large designs – Compile million gates under 1.5 hours in 1999 STAMP models for board-level static timing analysis  Guided iterations for synthesis designs — only changed modules must be re-placed and rerouted — reduces runtime and verification time for unchanged modules

Design Methodology

Virtex IP Roadmap

PCI

PC164/33 PC132/33 PC164/66 PC132/66 64-bit Bridge with FIFO & DMA 32-bit Bridge with FIFO & DMA Power Management

Memory Library

Single-Port BlockRAMs Dual-Port BlockRAMs Single-Port Distributed RAMs Dual-Port Distributed RAMs Synchronous FIFOs Asynchronous FIFOs

Math Library

Combinatorial Multipliers Pipelined Multipliers Constant Coefficient Multipliers

Reference Design

1Q99 1Q99 1Q99 Now Now

LogiCORE with Smart-IP

1Q99 1Q99 2Q99 2Q99 Now Now 2Q99 2Q99 2Q99 2Q99 2Q99 2Q99 2Q99

Design Methodology

Virtex IP Roadmap

Filter Library

FIR Building Blocks FIR Filters FFT

Bus Application Library

SDRAM Controller DMA Controller PowerPC Interface UART 82xx Cores

Communication Library

Reed Solomon Encoder Reed Solomon Decoder Viterbi HDLC 622 MBPS SONET

Image Processing Library

JPEG Encoder

Reference Design

1Q99 1Q99

LogiCO RE with Smart-IP

2Q99

Allianc eCO RE

2Q99 1Q99 2Q99 1Q99 1Q99 1Q99 1Q99 1Q99 2Q99 2Q99 2Q99 2Q99

Design Methodology

Xilinx IP Center

Web-Based Resources

 Core solutions — What’s new — IP catalog – LogiCORE – AllianceCORE — — — – reference designs Products and services Departments – PCI – – DSP telecom Tools – Core Generator – PCI configuration demo

www.xilinx.com/ipcenter

Design Methodology

High-Density FPGA Leadership

Addressing the Challenges

 Development platforms — SmartIP technology - predictable, high performance, flexible — Modular design - enables “system level FPGA” — Virtex - predictable high speed, high density, fast flexible I/O, RAM  Software methodologies — Open development system - joint development, early access — — — ASIC like design flows - min delays, pro-rate temp, verification flow Access to device resources Speed and area - technology independent, optimized for Improved productivity - faster compile times, better performance

Design Methodology

High-Density FPGA Leadership

Addressing the Challenges

 Design Implementation — Xilinx CORE Generator - Smart-IP technology, predictable, high performance, flexible, updateable from the Xilinx web site — — — — Complete & Compliant PCI - 64/66MHz, low cost 32/33MHz, synthesizable bridge, prototyping boards & drivers Complete DSP Solutions - fast, low cost, low power, slew of DSP Cores, system level tools & prototyping boards AllianceCORE Partnerships - focused on vertical solutions, over 25 partners, over 50 cores, verification tools & prototype boards Multi-Level Support Xilinx design center - expert FAE, 3rd party consulting, XPERTS,

Design Methodology