Transcript Fractal Formosa

Fractal Technologies
FreePDK45nm Library Validation
7/16/2015
Fractal Technologies
Confidential
Formats checked
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Formats of FreePDK45nm library checked by Crossfire:
– GDSII
– LEF
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Cell data + technology in one file
– Liberty
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3 process corners (best, typ, worst)
– Verilog
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3 process corners (best, typ, worst)
– Spice
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5 formats (pre_spice (2), spice, post_spice(2))
Custom created parser
– Doc (HTML)
– Schematic (xpm files)
Additional formats supported
– OpenAccess, Cadence, MilkyWay, TLF, PLIB
7/16/2015
Quality in Design Formats
2
Cell-presence (1)
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Using cell-lists provided with library:
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Schematics.lst (107 cells)
Fills.lst (6 cells)
Cell presence check
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GDSII:
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Found all Schematic and Fill cells
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LEF
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Liberty
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Best: Found all Schematic and Fill cells
Typ: Found all Schematic and Fill cells
Worst: Found all Schematic and Fill cells
Spice
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Best: Found all Schematic and Fill cells
Typ: Found all Schematic and Fill cells
Worst: Found all Schematic and Fill cells
Verilog
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Found all Schematic and Fill cells + Via1 Via2 (from technology)
Pre (single file + cell based): Found all Schematic and Fill cells
(cell based): Found all Schematic and Fill cells
Post (single file + cell based): Found all Schematic and Fill cells
Docs
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7/16/2015
All schematic and all Fill cells found
Quality in Design Formats
3
Terminals & Pins
• Are the same pins defined in all formats?
– Used Verilog (Typ) as Golden Reference
• Pins of the same name and direction found in:
– Liberty (3 corners)
– Verilog (3 corners)
– Cell Documentation
• VDD/VSS terminals are additional in :
– LEF
– Spice ( 6 formats)
Golden
Reference
Checked
Format
• No pins:
– GDSII
7/16/2015
Quality in Design Formats
4
Pin-Labels
• Do pins defined in the GR have text labels in the
checked formats
– Used Veriliog (typ) as golden-reference
• All pins from Verilog_typ are found as labels in:
– GDSII
• Has VDD, VSS labels but Verilog (Typ) has no VDD,VSS
pins
• All pins have labels in M1 (“11 0”)
– All other formats have no text labels (no check needed)
7/16/2015
Quality in Design Formats
5
Nets
• There are no formats with a “net” concept.
– Normally these are Cadence-DFII and MilkyWay
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Quality in Design Formats
6
Layout vs. layout
• Checks identity between polygons: layout-vs-layout or
abstract-vs-layout
– Performs Boolean mask XOR operations
– Detailed check example:
• “M1 drawing”+”M1 pin” in layout
== “M1 net”+”M1 boundary” in abstract
• Performed only 1 check for M1
– GDSII vs LEF
• M1 in GDSII is equal to M1 in LEF
– Other formats not relevant (no layout information)
7/16/2015
Quality in Design Formats
7
LEF cells Check
• Checks if LEF cells have the correct size acc. To
LEFtech
– ALL cells OK
– Parsing issues for LEF 5.6
• NAMECASESENSITIVE, DIRECTION in VIARULE and turn-via are
obsolete in LEF 5.6
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Quality in Design Formats
8
Routability
• Checks if signal-pins can be routed to cell-boundary
– Uses fast internal gridded maze router
– Users select layers (e.g. M1 only) or special rules (e.g.
double-via’s on outputs of high-drive cells)
– Technology settings (rules, vias, pitch) read from LEF
technology
– All pins of all cells routable in M1 and M2
• Totally 113 cells with 461 pins
• M1 only: 373 pins are not routable
• M1 and M2: 312 pins not routable (not on grid)
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Quality in Design Formats
9
Abutment
• All cells checked for self-symmetry and left/right
abutment (alignment on cell-boundary) with reference
cell (FILLCELL_X1):
– layers: M1 CONTACT NWELL PWELL PIMPL NIMPL DIFF
M2
– Formats: GDSII
– No errors found
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Quality in Design Formats
10
Functional Equivalence(1)
• Verified functional equivalence between Verilog, SPICE,
and Liberty
– Checks equivalence of Boolean expressions from different
databases
– For SPICE, expressions are automatically extracted from
the circuit
• All Verilog files are equal for the functions
• All Liberty files are equal for the functions
• Liberty_typ is equal to Verilog_typ
7/16/2015
Quality in Design Formats
11
Functional Equivalence(2)
• Verilog_typ/Liberty vs spice
– DFFRS_X1 flipflop has non matching QN output with
Verilog/Liberty when SN and RN are low and CK 0->1
– Verilog UDP table
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table
// SN
1
?
1
?
1
1
?
1
0
*
?
endtable
endprimitive
RN nextstate
?
0
r
1
1
r
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0
*
1
1
*
1
*
?
1
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f
0
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*
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1
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1
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CK NOTIFIER
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:?:
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:?:
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:0:
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:1:
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:?:
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:?:
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:?:
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:0:
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:?:
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:1:
*
:?:
: @IQ :
IQ
0;
1;
0; // reduce pessimism
1; // reduce pessimism
-; // Ignore all edges on nextstate
-; // Ignore non-triggering clock edge
0; // RN activated
0; // Cover all transitions on RN
1; // SN activated
1; // Cover all transitions on SN
x; // Any NOTIFIER change
– This means when RN = 0 (and SN = 0) => IQ = 0
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Quality in Design Formats
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Functional Equivalence(3)
• Verilog netlist is:
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seq4(IQ, SN, RN, nextstate, CK, NOTIFIER);
and(IQN, i_352, i_353);
not(i_352, IQ);
not(i_353, i_354);
and(i_354, i_355, i_356);
not(i_355, RN);
not(i_356, SN);
buf(Q, IQ);
buf(QN, IQN);
buf(nextstate, D);
– This means QN is anded with RN so QN should remain 0
when RN=0
• Crossfire output
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V:lib0791: 'DFFRS_X1': Equations for terminal 'QN' of format 'pre_spice_1file':
QN=!RN*SN + !RN*CK + SN*CK*!z51 + SN*!CK*z56
z51=!SN + D*!CK + RN*CK*z51
z56=!RN + SN*CK*!z51 + SN*!CK*z56
E:xpr0301: 'DFFRS_X1': Result for output 'QN' is different in '2' situations,
e.g. when 'CK 0->1‘
– This means that QN 0->1 when CK 0->1 and RN is 0
7/16/2015
Quality in Design Formats
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Functional Equivalence(4)
• Just to be sure this was simulated with a spice simulator
– Plots Q and QN
– SN and RN = 0
– CK 0->1
• Same for:
– DFFRS_X2
– SDFFRS_X1
– SDFFRS_X2
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Quality in Design Formats
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Functional Equivalence(5)
• Advantage of functional equivalence checker
– Not simulation based
• No test vectors needed.
• Completeness
• Runs much faster than simulation based.
– Seconds instead of hours
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Quality in Design Formats
15
Timing Characterization (1)
• Check if all timing arcs exists
– Identical timing arcs for all Liberty files
– Identical timing arcsfor all Verilog files
– Liberty misses many conditional timing arcs compared to
verilog_worst, verilog_best
• 88 cells miss conditional timing arcs in Liberty
– All liberty formats have same conditional timing arcs as
Verilog_typ.
• But verilog file is called “conditional” while data is non
conditional?
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Quality in Design Formats
16
Timing Characterization (2)
• Missing liberty conditional timing arcs (e.g. XOR2_X2)
– Verilog (best): (Line 3218)
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if((B == 1'b0)) (A => Z) = (0.1, 0.1);
if((B == 1'b1)) (A => Z) = (0.1, 0.1);
if((A == 1'b1)) (B => Z) = (0.1, 0.1);
if((A == 1'b0)) (B => Z) = (0.1, 0.1);
– Liberty (best): (Line 36103)
• Has unconditional positive unate nagetive unate
• Can negative/positive unate arcs in liberty backanotate to
conditionalarcs in Verilog.
– We think not if it can this is not really an error
7/16/2015
Quality in Design Formats
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Timing Characterization (3)
• Sanity of timing tables: increasing output delays/slopes
for increasing output load and input slope
– Verilog files have unit delays 0.1 (not relevant)
– Liberty (best,typ,worst) Only Combinational cells (87 cells)
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Tol = 0 check for input slope: 623 “errors”
Tol = 0.001 check for input slope: 199 “errors”
Tol = 0.01 check for input slope: 12 “errors”
Tol = 0.02 check for input slope: 7 “errors” (e.g. INV_X4)
Values ("0.013633,0.023350,0.035602,0.060068,0.109005,0.206889,0.402654", \
"0.017153,0.026818,0.038993,0.063468,0.112409,0.210290,0.406057", \
"0.024415,0.034125,0.046302,0.070784,0.119730,0.217613,0.413381", \
"0.036563,0.048854,0.061043,0.085523,0.134469,0.232353,0.428122", \
"0.054698,0.073899,0.089990,0.114984,0.163890,0.261754,0.457513", \
"0.080636,0.111707,0.136740,0.171835,0.222779,0.320536,0.516236", \
"0.114776,0.166411,0.206753,0.261525,0.335066,0.438350,0.633787", \
"0.152770,0.239871,0.306848,0.395445,0.510524,0.661333,0.869488", \
"0.179502,0.325039,0.437882,0.585366,0.771983,1.008238,1.313759", \
"0.158913,0.393652,0.581726,0.829933,1.141021,1.524609,2.003528");
7/16/2015
Smaller Value!
Quality in Design Formats
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Timing Characterization (4)
• In general: timing table values increase with increasing
output loads.
– Tol = 0 Check for output cap only: 0 “errors” (all liberty
files)
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Quality in Design Formats
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Custom defined DS – Document
• Document format parser was created in an hour (python)
<Cell Name="AND2_X1"
CornerName="typical_conditional.lib"
LibFile="liberty_typical_conditional.lib.xml">
<Schematic>images/AND2_X1.png</Schematic>
<Navigation>
<Parent Name="Table of Contents" Link="../CornerList.xml"/>
<Next Name="AND2_X2"
Link="AND2_X2_typical_conditional.lib.xml"/>
</Navigation>
<GenChars>
<Strength>
1</Strength>
<Type>
Combinational</Type>
<Input>
A1</Input>
<Input>
A2</Input>
<Output>
ZN</Output>
</GenChars>
<Name>
"AND2_X1"</Name>
7/16/2015
if (len(words) >= 2) and (words[0:2] == ['Cell', 'Name']):
cellList = []
cellname = words[2]
print 'CellName: ', cellname
cellList = cellList + [cellname]
outputs = []
if cellname not in CELLLIST:
CELLLIST = CELLLIST + [cellname]
cell[cellname] = library.addCell( cellname )
cv[cellname] = cell[cellname].addCellview ( '' )
if ((l>=2) and
((words[1] == '/Input') or (words[1] == '/Output') or (words[1]
== "/InOut"))):
for cellname in cellList:
pin = words[0]
pin_dir = words[1]
print 'Pin: ', pin, pin_dir
DIR = 'UNKNOWN'
if pin_dir == '/Input' : DIR = 'INPUT'
if pin_dir == '/Output' :
DIR = 'OUTPUT'
if not pin in outputs: outputs = [pin] + outputs
if pin_dir == '/InOut' : DIR = 'BIDIRECTIONAL'
term = cv[cellname].addTerminal( pin )
term.setDirection(DIR)
pin = term.addPin()
Quality in Design Formats
20
Conclusions
• Quality of this library looks pretty good.
• FreePDK45nm library contains very few inconsistencies if any
– LEF 5.6 obsolete statements
– Functional Difference between spice verilog/liberty
(S)DFFRS_X1/2
– Liberty vs Verilog timing arc issues
– Decreasing value entries in the liberty timing tables
– Grid-less router needed
7/16/2015
Quality in Design Formats
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