Transcript 8085 Architecture & Its Assembly language programming

Dr A Sahu
Dept of Computer Science &
Engineering
IIT Guwahati
Hierarchy of I/O Control Devices
8155
I/O + Timer
8253/54
Timer
6 mode timer
8259
Interrupt controller
2 Port (A,B),
No
Bidirectional
HS mode (C)
4 mode timer
8255
I/O
8237
DMA controller
2 Port (A,B)
A is Bidirectional
HS mode (C)
Extra controls
8251
Serial I/O USART
controller
• 8155 I/O Interface & Timer
– Dedicated I/O interface (8255)
– Dedicated Timer (8254/8253)
• 8255 Ports and mode of operations
• Interfacing A/D Converter using Handshake
mode using 8255
• IO Capability:
– 2kbits static RAM 256x8
– 2 programmable 8 bit I/O ports
– 1 programmable 6 bit I/O port
Reset in
RD
WR
C
IO/M
E
D6
Timer
Command
Mode
00
Mode
01
Mode
10
Mode
11
D5
D4
IEB
IEA
D
3
D2
PC
N/2
N/2
N/2
N/2
D1
D0
PB
PA
N/2
N/2
N
N
PB0PB7
AL
E
– 1 programmable 14 bit binary
counter/timer
– 4 Modes
N
PA0PA7
Port
B
RAM
AD0-AD7
• Timer Capability:
D7
Port
A
Port
C
Timer
CLK
PC0-PC5
Timer
MSB
LSB
Timer
Out
A
L
T
D
3
D
2
PC5
PC4
PC3
PC2
PC1
PC0
1
0
0
IN
IN
IN
IN
IN
IN
2
0
1
OUT
OUT
OUT
OUT
OUT
OUT
3
1
0
OUT
OUT
OUT
STBA
BFA
INTRA
4
1
1
STBB
BFB
INTRB
STBA
BFA
INTRA
CEb
CWR
A2
A1
A0
Port (ALE
high,
AD0=A0)
0
0
0
Command
/Status
Register
0
0
1
PA
0
1
0
PB
0
1
1
PC
1
0
0
Timer LSB
1
0
1
Timer MSB
AD0-AD7
Latch
ALE
A2
D7-D0
Port
A
A0-A7
A1
A0
0
1
3 to 8 2
3
Decoder 4
5
PA0-PA7
Port
B
PB0-PB7
Port
C
PC0-PC5
Timer
MSB LSB
Clock for timer
Timer
Out
Block Diagram of 8255
CSb
A1
A0
Sel
0
0
0
Port A
0
0
1
Port B
0
1
0
Port C
0
1
1
CRW
Bi directional
Data Bus
D7-D0
RDb
WRb
A1
A0
RESET
CSb
Data
Bus
Buffer
Read
Write
Control
Logic
Group A
Control
8 bit Internal
Data Bus
Group B
Control
Gr A
Port A
(8)
I/O
PA7-PA0
Gr A
Port C
(H 4)
I/O
PC7-PC4
Gr B
Port C
(L 4)
I/O
PC3-PC0
Gr B
Port B
(8)
I/O
PB7-PB0
Ports & Modes in 8255
Port A
8255
CU
CL
Port B
Port C
D7 D6
0/1
BSR Mode
Bit Set/Reset
BSR Mode
Bit Set/Reset
For Port C
No Effect on
I/O Mode
D5
D4 D3 D2 D1 D
I/O Mode
Mode 0
Simple I/O
for Ports
A, B & C
Mode 1
HS mode
for Ports
A and/or B
Mode 2
Bidirectional
Data mode for Port
A
Port C bits
are used for
HS
B can in mode 0/1
Port C bits are used
for HS
Ports & Modes in 8255 : Control register
7
D7
6
D6
5
D5
4
3
2
1
0
D4
D3
D2
D1
D0
Group B
Port C(L) – 1 Input
0 output
Port B – 1 Input 0 output
Mode select: 0 mode 0; 1 mode 1
Port C(U) – 1 Input 0 output
Port A – 1 Input 0 output
1 – mode select
0 – bit set/reset
Mode select: 00 mode 0;
01 mode 1; 0x mode 2
Group A
I/O port Addressing
A7
A6
A5
A4
A3
A2
Port A=80H
CSb
8255
A1
A0
A1
A0
IORb
IOWb
RDb
WRb Reset
Port C=82H
Port B=81H
Reset
CSb
A1 A0
HEX Address
Port
A7 A6 A5 A4 A3 A2
1 0 0 0 0 0
A1 A0
0
0
= 80H
A
0
=81H
B
1 0
=82H
C
1 1
=83H
Control Register
1
BSR (Bit Set or Reset Mode)
• Set/Reset bit of Port C
• Heavily used for HS and Interrupt mode
• BSR Control word
D7
D6
D5
D4
0
BSR
Mode
Not used, So (000)
D3
D2
Bit Select
• BSR Control word
– To set PC7= 0 000 111 1 (0FH)
– To reset PC7= 0 000 111 0 (0EH)
– To set PC3 = 0 000 011 1 (07H)
D1
D0
S/R (1/0)
Ports
• Control register controls the overall operation of
8255
• All three ports A, B and C are grouped into two
Group A
Port A
Group B
Upper C
Lower C
Port B
Operation modes
• 8255 has three modes:
- mode 0: basic input-output
- mode 1: strobed input-output
- mode 2: strobed bidirectinal bus I/O
• In mode 0
- two 8-bit ports and two 4-bit ports
- any port can be input or output
- Outputs are latched, inputs are not latched
Mode 0
Port A
Upper C
Lower C
Port B
Operation mode 1
• In mode 1:
-three ports are divided into two groups
-each group contains one 8-bit port and
one 4-bit control/data port
- 8-bit port can be either input or output
and both latched
- 4-bit port used for control and status of 8bit data port
Mode 1
Group A
Port A
Group B
Upper C
Lower C
Port B
Operation mode 2
• In mode 2
- only port A is used
- port A becomes an 8-bit bidiectional bus
- port C acts as control port (only pins PC3-PC7 are used)
Mode 2
Group B
Group A
Port A
C7-C3
Port B
Programming 8255
 Mode 2:
— Port A is programmed to be bi-directional
— Port C is for handshaking
— Port B can be either input or output in mode 0 or mode 1
PC7
PC6
PC4
8255 PC5
PC3
PC0
PC0
PC0
PA[7:0]
OBFA
ACKA
STBA
IBFA
INTRA
PB[7:0]
In
In
In
Out
Out
Out
Mode 0
STBB
IBFB
INTRB
OBFB
ACKB
INTRB
Mode 1
• R S Gaonkar, “Microprocessor
Architecture”, Chapter 15