Transcript RQI Poster - Rice University

Search for Superconductivity with Nanodevices
Precious Cantu1, Takahiro Nishijima2, Hidekazu Shimotani2, and Yoshihiro Iwasa2
1NanoJapan Program 2009 and Department of Electrical Engineering, Louisiana State University, Baton Rouge, LA, USA
2Institute for Materials Research, Tohoku University, Sendai, Japan
Results cont’d
Methods cont’d
Introduction
Background:
Ti (10 nm thick)
2. Comparison of HH-P3(CΞC-Dec)Th
Au (70 nm thick)
FET & EDLT Transfer Characteristic Curves
Electric Double Layer
Transistor
Conventional FET
0.15
7
On Current:

0.12
On Current:

6
5
(500 nm thick)
0.09
0.06
0.03
0.00
-150
EDL
formed
－
＋
＋ ＋ ＋－ ＋
＋ －
＋
＋
－ ＋
－
－
－
－
－
－ －
＋
－
＋－
S
D － － －
+ + + + + +
4
3
1
Off Current:

0
-100
-50
0
50
100
-3.0
-2.5
VG (V)
SiO2
Si back gate
-2.0
-1.5
-1.0
VG (V)
3. Comparison of P3HT & HH-P3(CΞC-Dec)Th Conductance
1 mm
sample
P3HT
Conductance
0.40
Measurement Apparatus:
Conductance (S)
Gate Induced insulator-to-metal Transition and Superconductivity
K. Ueno et al.,
Nat. Mater. 7, 855(2008)
EDLT 0.36 S
Conductance increases
Superior Advantage
0.30
0.25
0.20
0.15
0.10
0.05
HH-P3(C=C-Dec)Th
Conductance
7
0.35
Notable Research:
H. Shimotani et al.,
Appl. Phys. Lett. 91, 082106(2007)
EDLT ID is 47 times larger
Off Current is smaller
2
Off Current:
n
Conductance (S)
＋
VG
applied
VG = 0
－ －Gate－
－
ID (A)
SiO2
Si back gate
ID (A)
SiO2
Si back gate
6
EDLT 6.14 S
Conductance increases
Superior Advantage
5
4
3
2
1
FET 0.027 S
FET 0.042 S
0.00
0
-100
-80
-60
-40
-20
0
-100
-80
VG (V)
Probe Station
-60
-40
-20
0
VG (V)
4. FET Carrier Motilities of P3HT & HH-P3(CΞC-Dec)Th
L
dID
μ
WCVDS dVG
Aim: To realize superconductivity in materials that have not been reached by
conventional chemistry
Results
one order larger
1. Comparison of P3HT FET & EDLT Transfer Characteristic Curves
Methods
Conclusion and Future Work
40
Materials and Device Fabrication
P3HT Structure
HH-P3(CΞC-Dec)Th Structure
30
Ionic Liquid
ID (A)
Semiconductors
Demonstrated the first field-effect transistor (FET) operation of HH-P3(CΞC-Dec)Th.
20
On Current:

The modulation of conductance in the electric double layer transistor (EDLT) was increased
compared to the conventional FET in both polymers, however with poor mobility yield.
Future work will focus on optimizing fabrication techniques such as:
Drop cast conditions
Annealing temperature
Introduce spin coating
This should improve the crystallinity of the polythiphene films, which may enhance the
mobility, and thus the conductivity. This should aid in the metallization of the materials
EDLT ID is 152 times larger
Off Current is smaller
10
Off Current:
2 nA
0
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
Electron hopping
Slower mobility
Coplanar Structure
Well-stacked
VG (V)
0.2
Acknowledgement
0.4
This material is based upon work supported by the National Science Foundation under
Grant No. OISE-0530220