Transcript Lecture 8 Control Unit

Lecture 5
Control Unit
Implementation
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 1
6-Step Instruction Cycle
Memory
Access time
[1]
[2]
[3]
Memory
Access time
[4]
[5]
[6]
Control Unit Implementation
MAR
PC(address), M
R(control)
…
...
IR
MBR(OP-code)
Decode instruction
Control Signal Generator
IR,
Address Processor
MBR(address)
MAR
Effective Address, M
R/W
…
...
Data path activation to do operation
Decide final PC by this time,
go to [1] for the next instruction
CS510 Computer Architectures
Lecture 5- 2
Micro-Operation
Rd:
Rs1, Rs2:
Destination Register
Source Register
CPU data path
Micro-operation
Rd
Register
File
f(Rs1, Rs2)
Simple data move:
Unary operations:
Binary operations:
Rd
Rd
Rd
ALU
f
fI(Rs1, f)
fu(Rs1, f)
fb(Rs1, Rs2)
A Micro-operation generates a finite set of Control Signals at the
proper time according to the Machine State and the Control Data to
activate the Micro-actions and to update the Control Data Structure.
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 3
Micro-Action/Micro-Operation
Micro-action
Register
ALU
f
- An Activation of a part of data path
File
Bus
Register Output
Register Input
Bus
- Selection of a function of the Functional Unit(ALU), Memory
ALU:
ADD, OR, SHR, etc
Memory: R(read), W(write)
Micro-operation
- A micro-operation can be described in terms of a sequence of
micro-actions
Rd
Control Unit Implementation
fADD(Rs1, Rs2)
Input Bus 1
Rs1
Input Bus 2
Rs2
ADD
Rd
Output Bus
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Lecture 5- 4
Activation of Micro-action:
An Example
Rd
fADD(Rs1, Rs2)
Input Bus 1
Rs1
Input Bus 2
Rs2
ADD
Rd
Output Bus
Input Bus 1
Input Bus 2
Rs1
ADD
SUB
Rs2
ALU
...
Rd
AND
Output Bus
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 5
Control Point
Control Point:
Hardware locations(gates) to which control signals
are applied to achieve the intended set of functions
(a sequence of micro-operations, each of which
may also be a sequence of micro-actions)
• Register In-Gates
• Register Out-Gates
• ALU function selection terminals
• Memory read/write control signal terminal
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 6
Control Points:
Register In-Gate and Out-Gate
Load R1
R1
…
Q
...
R2
…
Q
...
R3
…
Q
...
Send R1
Send R2
Send R3
…
D
Load R3
…
D
...
…
D
...
Bus
Register Out Gates
Control Unit Implementation
R1
Load R2
...
R2
R3
Register In-Gates
CS510 Computer Architectures
Lecture 5- 7
Control Points:
ALU Function Selection Points
X
Y
Cc
A
PS
C
DI
C0
Cm
Logic
Unit
Adder
AN
AO
Cr
Ri
Li
Ro
Lo
Shifter
NS
LS
RS
SE
Z
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 8
Independent Control Point
Example:
32-bit machine with 8 registers
ALU has 4 different functions in 32-bit data in parallel
Memory has 1 terminal for R/W
No. of Control Points:
(32 x 8 x 2) + (32 x 4) + 1 = 641
No. of Independent Control Points
(8 x 2) + 4 + 1 = 21
During an instruction execution, usually a group of bits are
transferred together as an information
Instruction: OP-code, Register Address, Memory Address
Floating point numbers: Sign bit, Exponent, Mantissa
Others: A number, A character or a character string
Each of these groups actually need an identical control signal for
each bit within the group
-> Each
Control Unit Implementation
group is associated with one Independent Control Point
CS510 Computer Architectures
Lecture 5- 9
Independent Control Points:
Around MBR
MBR
BUS
BUS
MBR(OP )
BUS
MBR(A)
MBR
MBR(O)
MBR(A)
15
...
BUS
BUS
5
MBR(O)
To ALU
6
MBR
BUS
5
MBR
...
M
0
...
M
0
...
MBR
BUS
Memory Bus
From ALU
15
...
M
Control Unit Implementation
M
MBR MBR M
BUS
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... ...
MBR M
... ...
BUS
MBR(A)
Lecture 5- 10
Micro-Operation Timing
•
Execution Time of a Micro-Operation - Micro-Cycle
Time required to change the information in a set of registers
•
CPU Clock is the most basic timing signal used for the reliable
operation of CPU and CPU Clock Cycle is equal to the Micro-Cycle
•
Information need to be stored in a register at the end of each
micro-cycle, otherwise, information will be lost
•
Micro-Cycle is determined by the characteristics of FF’s(setup
time, hold time, delay) used in registers and the propagation delay
of the circuits (ALU) in between the source and destination
registers
– Micro-Cycle may vary depending on the micro-operation
» Signal path, Type of ALU operation
Control Unit Implementation
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Lecture 5- 11
Micro-Cycle
•
•
Synchronous Fixed: There is only one Micro-Cycle, i.e., all microoperations’ execution times are assumed to be identical
Synchronous Variable: Certain long micro-operations are allowed to
take multiple cycles without causing a state transition, i.e., different
micro-cycle lengths are allowed
– e.g. Consider the different time requirements by R <- fI(R) and R <- fb(R, R)
•
Asynchronous:
No clock or external mechanism that determines a
state transition. Hardly used to control the execution of instructions
Micro-Cycle Time
It can be broken down into Control Time and Data Path Time
– Control Time
» Time to decode control data and generate control signals
– Data Path Time
» Time to transmit control signals and transfer data
– Control Time and Data Path Time are partially overlapped in some
high performance machines
Control Unit Implementation
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Lecture 5- 12
Generation of Control Signals
Control Data
Machine State
Control Rule
Control Signal
Timing
Microprogram or
Combinational logic circuit
E.g. In state(Machine Cycle) S1, at time(timing state) t1: R1
f(R2, R3)
Clock
IBus1
R2, IBus2
R1
R3
f
OBus
S1
Machine Cycle
Timing State
Control Unit Implementation
t1
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Lecture 5- 13
Intra-Instruction Sequencing
Instruction
Fetch
Instruction
OP-code
Decode
Instruction
Address
Decision
Control Unit Implementation
Operand
Store
Operand
Fetch
Operation
Specified
Operand
Address
Compute
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Operand
Address
compute
Lecture 5- 14
RISC-S Architecture
IBus1
IBus2
IR
Memory
MAR
PC
MBR
Register
File
ALU
+4
OBus
Instruction =4 bytes
Rd
fu(Rs1)
Rd
Rs1
PC
MBR
MBR
PC
MAR
R
IR
R
Control Unit Implementation
Rd
Rd
MAR
PC
R
fb(Rs1, Rs2)
Rs1, Rs2
(R, R)
(R, IR(addr))
(PC, IR(addr))
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f
Numerical Calculation
Logical Calculation
Shifts
+4
Lecture 5- 15
Instruction Set - RISC-S
Instruction
ADD
SUB
AND
OR
SLL
LD
ST
JMP
CALL
RET
Operand
Rs1, Rs2(S2), Rd
Rs1, Rs2(S2), Rd
Rs1, Rs2(S2), Rd
Rs1, Rs2(S2), Rd
Rs1, Rd
S2(Rs1), Rd
S2(Rs1), Rd
COND, S2(Rs1)
Rd, S2(Rs1)
S2(Rs1)
Operation
Rd
Rs1 + Rs2
Rd
Rs1 - Rs2
Rd
Rs1 ^ Rs2
Rd
Rs1 v Rs2
Rd
logical Shift Left(Rs1)
Rd
M[Rs1 + S2]
M[Rs1 + S2]
Rd
(COND=1): PC
Rs1 + S2
Rd
PC, next PC
Rs1 + S2
PC
Rs1 + S2
Representative Instructions
ADD
SLL
LD
JMP
Rs1, Rs2, Rd
Rs1, Rd
S2(Rs1), Rd
COND, S2(Rs1)
Control Unit Implementation
Integer Addition
Logical Shift Left 1 bit
Load a word
Conditional Branch
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Lecture 5- 16
Micro-Operations for RISC-S
[1]
[2]
[3]
[4]
[5]
ADD
MAR
PC, R;
PC
PC + 4;
IR
MBR;
Decode IR;
Rd
Rs1 + Rs2;
[6]
[7]
Control Unit Implementation
SLL
MAR
PC, R;
PC
PC + 4;
IR
MBR;
Decode IR;
Rd
shl Rs1;
LD
MAR
PC, R;
PC
PC + 4;
IR
MBR;
Decode IR;
MAR
Rs1 + S2, R;
JMP
MAR
PC, R;
PC
PC + 4;
IR
MBR;
Decode IR;
T/F(test condition),
T: PC Ts1 + S2;
...
Rd
MBR;
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Lecture 5- 17
Control Unit Implementation
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Lecture 5- 18
Control Unit Implementation
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Lecture 5- 19
Control Unit Implementation
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Lecture 5- 20
Major State - Machine Cycle
During a Major State, a memory reference is made, i.e. a Machine Cycle
includes a Memory Cycle
FETCH:
Read an instruction from memory specified by the address in
PC, and whatever left to do before making transition to FETCH,
EXECUTE, or INDIRECT machine cycle
EXECUTE: For the instructions with an operand in memory, read operand
to perform operation specified in the instruction, and make a
transition to FETCH machine cycle
INDIRECT: Read effective address from memory, and make a transition to
FETCH or EXECUTE machine cycle - not happen in RISC
2g-address instruction:
R
f(R, R)
When does the operation(f) take place ?
(1+X)- or (1+g+X)-address instruction:
When does the address calculation take place?
Control Unit Implementation
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Lecture 5- 21
Machine Cycles
R-to-R, JMP(direct address)
FETCH
Memory Reference
EXECUTE
Memory Reference(Indirect address)
JMP Indirect
INDIRECT
RISC-S does not have
Indirect Machine Cycle
INTERRUPT
Interrupt
Control Unit Implementation
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Lecture 5- 22
Machine State Register
(Major State Register)
Major State
Q1 Q0
FETCH
0 0
INDIRECT
0 1
EXECUTE
1 0
INTERRUPT 1 1
Q0
Q1
FET←INT
INT←FET
INT←EXE
EXE←FET
INT←FET
FET←INT
FET←EXE
FET←FET
FET←EXE
EXE←FET
INT←EXE
FET←FET
t3
J
Q0
FF0
K
Q0'
J
Q1
FF1
K
Q 1'
FET
IND
Clock
EXE
INT
Control Unit Implementation
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Lecture 5- 23
Timing State
Timing State Counter - A counter that advances for each CPU clock pulse
- Counter advances in the period of Micro-cycle
- Counter resets at the maximum count, i.e., at the
beginning of each Machine Cycle
CPU Clock
Machine Cycle
t0
t1
t2
t3
Memory Cycle
(Memory Active)
Memory Access time
(Read Data available)
A timing state counter counts from 0 to 3
Control Unit Implementation
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Lecture 5- 24
Machine Cycle:
Various Addressing Modes in AC Machines
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
t0
t1
t2
t3
t0
t1
t2
t3
t0
t1
t2
t3
Immediate Address
ADD #X
MAR
MBR, R;
PC
PC + 4;
IR
MBR, Decode;
MBR AC+MBR(A);
PC Relative Address
ADD $X
MAR
MBR, R;
PC
PC + 4;
IR
MBR, Decode;
MBR PC+MBR(A);
MAR
MBR, R;
AC AC + MBR;
-
Direct Address
Indirect Address
ADD X
ADD @X
MAR
MBR, R; MAR
MBR, R;
PC
PC + 4;
PC
PC + 4;
IR
MBR, Decode; IR
MBR, Decode;
MBR MBR(A);
MBR MBR(A);
MAR
MBR, R; MAR
MBR, R;
AC AC + MBR;
MAR
MBR, R;
AC AC + MBR;
-
FETCH; INDIRECT; EXECUTE
Notice that memory cycle is 4 times slower than the micro-cycle(3 micro-cycle Access
Time), and that 4 micro-cycle machine cycle is possible with a faster memory.
Control Unit Implementation
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Lecture 5- 25
Machine Cycle - RISC-S
t0
t1
t2
t3
ADD
MAR
PC, R;
PC
PC + 4;
IR
MBR, Decode;
Rd
Rs1 + Rs2,
SLL
MAR
PC, R;
PC
PC + 4;
IR
MBR, Decode;
Rd
shl Rs1,
RI: INTERRUPT,
RI’: FETCH;
RI: INTERRUPT,
RI’: FETCH;
t0
t1
t2
t3
LD
JMP
MAR
PC, R;
MAR
PC, R;
PC
PC + 4;
PC
PC + 4;
IR
MBR, Decode; IR
MBR, Decode;
MAR
Rs1 + S2, T/F(test condition),
T: PC
Rs1 + S2,
RI: INTERRUPT,
RI’: FETCH;
R;
Rd
MBR;
RI: INTERRUPT,
RI’: FETCH;
FETCH; EXECUTE
ALU Control
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 26
ALU Control
X
Y
Cc
A
PS
C
DI
C0
Cm
Logic
Unit
Adder
AN
AO
Cr
Ri
Li
Ro
Lo
Shifter
NS
LS
RS
SE
Z
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 27
ALU Control Micro-Actions
ICPs
Add
Increment
1’s Compl Add
2’s Compl Add
AND
OR
Compl AC
Left Shift
Right Shift
Pass
Clear AC
Clear C
Compl C
Control Unit Implementation
C0
0
1
0
1
d
d
0
0
0
d
d
d
d
Cm
0
0
1
1
d
d
1
d
d
d
d
d
d
A
1
1
1
1
0
0
1
0
0
0
0
0
0
DI
0
1
0
0
d
d
1
d
d
d
d
d
d
Cc
0
0
0
0
0
0
0
0
0
0
0
0
1
Cr
0
0
0
0
0
0
0
0
0
0
0
1
0
AN
d
d
d
d
1
0
d
d
d
d
d
d
d
AO
0
0
0
0
1
1
0
0
0
0
0
0
0
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PS
0
0
0
0
0
0
0
1
1
1
0
0
0
NS
1
1
1
1
1
1
1
0
0
1
0
0
0
LS
0
0
0
0
0
0
0
1
0
0
0
0
0
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
SE
1
1
1
1
1
1
1
1
1
1
0
0
0
Lecture 5- 28
Constraints on Concurrency
Micro-operation concurrency
– Hardware resource conflict
MAR
AC
MBR(addr)
AC + MBR
AC
MAR
AC’
MBR(addr) + IX
Bus conflict
– Register dependency
R2
R1
SHL(R1) These are not concurrent micro-operations
R2 + R3 even if Adder and shifter are independent units.
– However, multiple fan-out of registers may be OK
R2
R4
Control Unit Implementation
SHL(R1) These are concurrent micro-operations if Adder
R1 + R3 and shifter are independent units.
CS510 Computer Architectures
Lecture 5- 29
Instruction and Machine Cycles
Number of
Machine Cycles
1
2
3
4
5
6
Instruction
Stack Computer: Functional
AC Computer:
Unary Functional, Control not with Indirect Addr
GPR Computer: R-R instructions, Control not with Indirect Addr
Transfer and Control Instructions not with Indirect Address
AC Computer:
Functional
GPR Computer: R-M Instruction not with Indirect Address
Transfer Instruction with Indirect Address
AC Computer:
Functional with Indirect Address
GPR Computer: R-M Instruction with Indirect Address
M-M Instruction not with Indirect Address
M-M Instruction with 1 Indirect Address
M-M Instruction with 2 Indirect Address
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 30
Control Rules for RISC-S
State
FET.t0
FET.t1
FET.t2
Micro-Operations
MAR
PC, R;
PC
PC + 4;
IR
MBR, Decode;
FET.t3
(FU. XF’.CT’.IO’): Rd
f(Rs1, Rs2),
(FU’.XF. CT’.IO’): MAR
f(Rs1, S2),
(FU’.XF’.CT. IO’)^(T): PC f(Rs1, S2),
(FU’.XF’.CT’.IO): -;
EXE.t0
EXE.t1
EXE.t2
EXE.t3
(XF.LD): R, (XF.LD’): W;
(XF.LD’): MBR
Rd;
(XF.LD): Rd
MBR;
RI: INT, RI’: FET,
EXE,
RI: INT, RI’: FET,
RI: INT, RI’: FET,
Instruction Decode;
Functional: FU, Transfer: XF(Load: LD, Store: LD’), Control: CT, I/O: IO
Interrupt Request;
RI
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 31
Implementation Of CU
- Hardwired Implementation -
Major State
Rs1
SCC
Timing State
Rs2
S2(imm)
Rd
Control Data
Control Logic Circuit
Control Unit
Control Unit Implementation
CS510 Computer Architectures
Independent Control Points
Cond
...
OP-code
IR
Flag
Control Data
CPU
Lecture 5- 32
Control Unit Implementation
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Lecture 5- 33
Microprogrammed
Control Unit
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 34
Microprogrammed Control Unit
In this topic, we will study
– Micro-instruction
» Data path control and Sequence control information
» Vertical micro-instruction and Horizontal micro-instruction
– Microprogramming RISC-S
»
»
»
»
RISC-S Architecture and Instruction Set
Vertical micro-instruction format
Microprogramming with Vertical micro-instruction
Horizontal micro-instruction format
– Microprogram control unit
– Advantages and Disadvantages of microprogram
Control Unit Implementation
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Lecture 5- 35
Microprogrammed Control Unit
Micro-instruction
IR
Control Point
Control
Storage
Decoder
CSAR
U-program
Control
Unit
Flag
Status
of CPU
Branch Address
CPU
Control Unit
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 36
Micro-Instruction
•
Micro-instruction should contain
– Data Path Control information
» Information needed to generate control signals required to activate the data
path in the CPU to execute intended micro-operation(s)
» Representation of the data path control information
> Horizontal Micro-instruction - Direct micro-instruction
> Vertical Micro-instruction - Encoded micro-instruction
– Sequence Control information
» A part of information needed to generate the next micro-instruction address
» e.g., Branch address
•
•
One micro-instruction may contain both information,
Or, Two types of micro-instructions
– Data path control micro-instruction
– Sequence control micro-instruction
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 37
Horizontal Micro-Instruction
Each of the bits in the data path control information is directly connected to an
independent control point, i.e., each bit is associated with a micro-action
–
–
–
–
–
Data path control information field is very long
Decoder is not needed to generate control signals, decoding delay is absent
Very fast to execute a micro-instruction
Concurrent micro-operation can be specified if there are multiple data paths
However, in an ordinary machine, micro-instruction bit utilization is poor, thus
control storage utilization is inefficient
– Very high performance machines can only afford to have HM
0 1 2 3
n-1
Sequence Control
Control Points
CPU
Control Unit Implementation
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Lecture 5- 38
Vertical Micro-Instruction
Data path control information is represented by a set of fields,
each of which represents a set of micro-actions associated
with a similar hardware resources, e.g: INBUS1, OUTBUS, ALU,
Registers, Memory, etc
– Information in each field is encoded to reduce the microinstruction length, thus micro-instruction length is short
– Decoder is needed for each encoded field
– Concurrency is low, but micro-instruction bit utilization is
good, thus control storage utilization is efficient
– Generation of control signal is slow due to decoding delay
– Easy to make symbolic micro-instructions
– Most of commercially available machines employ VM
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 39
Encoding Control Information
• Direct Encoding
...
...
...
Sequence Control
...
...
• Indirect Encoding
...
Sequence Control
...
...
...
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 40
Micro-Action
• Micro-action that activates a data path
– Selection of a register whose content can be sent to a bus
» INBUS1
R2
– Selection of a register that stores the information on a bus
» R3
OUTBUS
• Micro-action that makes the selection of ALU function
– For 2’complement ADD
» A, C0, Cm, DI’, Cc’, Cr’, AO’, NS, SE
• Micro-action that activates the memory control
– Memory Read(R) and Write(W) control
» R(R) or R’(W)
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 41
Example - Architecture:
RISC-S
INBUS2
INBUS1
IR
MAR
Memory
PC
Register
File
MBR
ALU
Flag
+4
OUTBUS
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 42
Example - Instruction Set:
RISC-S
0
1
Cond
Op-code
31
OP-code
0 00 0000
0 00 0001
0 00 0100
0 00 0101
0 00 1000
1 01 0000
1 01 0001
0 10 0000
0 10 0001
0 10 0010
SCC
24 23
Symbol
ADD
SUB
AND
OR
SLL
LD
ST
JMP
CALL
RET
Rd
Rs2
imm13
Rs1
19 18
Operands
Rs1,Rs2,Rd
Rs1,Rs2,Rd
Rs1,Rs2,Rd
Rs1,Rs2,Rd
Rs1,Rd
S2,Rd
Rd,S2
CD,S2
Rd,S2
S2
S2
13 12
0
Operation
Rd
Rs1 +Rs2
Rd
Rs1 - Rs2
Rd
Rs1 ^ Rs2
Rd
Rs1 v Rs2
Rd
logical shift left Rs1
Rd
M[PC+S2]
M[PC+S2]
Rd
(COND=1):PC←PC+S2
Rd
PC, next PC←PC+S2
PC←PC+S2
F: Represents the Function of the instruction
T: Represents the Type of the instruction
000: Functional, 101: Transfer, 010: Sequencing
Control Unit Implementation
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Lecture 5- 43
Vertical Micro-Instruction for RISC-S:
Data Path Control
• Memory Control Field(M: 2 bits)
– Memory is either Read or Write, or No-operation, i.e. needs to
represent 3 kinds
M
00
01
10
11
NOP
Not used
W(Memory
MBR)
R(MBR
Memory)
• Arithmetic Function Control Field(AF: 2 bits)
– ADD, 2’ Complement ADD, Pass, Disable - needs to represent 4 kinds
AF
00
01
10
11
Control Unit Implementation
Disable
Pass
ADD(Rd
Rs1 + Rs2)
2’ complement ADD(Rd
Rs1-Rs2)
CS510 Computer Architectures
Lecture 5- 44
Vertical Micro-Instruction for RISC-S:
Data Path Control
• Logical Function Control Field(LF: 2 bits)
– AND, OR, Disable - needs to represent 3 kinds
LF
00
01
10
11
Disable
Not used
OR(Rd
Rs1 V Rs2)
AND(Rd
Rs1 ^ Rs2)
• Shift Function Control Field(S: 1 bit)
– Either shift left or pass the shifter - needs to represent 2 kinds
S
0
Pass
1
Shift left(Rd
SLL(Rs1))
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 45
Vertical Micro-Instruction for RISC-S:
Data Path Control
• Input Bus - INBUS1(IN1: 2 bits)
– MBR, PC, R(Rs1), Disable - needs to represent 4 kinds
IN1
00
01
10
11
INBUS2
INBUS1
Disable
INBUS1
INBUS1
INBUS1
PC
Rs1
MBR
IR
MAR
Memory
• Input Bus - INBUS2(IN2: 2 bits)
PC
MBR
Register
File
ALU
Flag
+4
OUTBUS
– R(Rs2), IR[imm13(S2)], IR[Rs2(S2)], Disable - needs to represent 3 kinds
IN2
00
01
10
11
Control Unit Implementation
Disable
Not used
INBUS2
INBUS2
IR(imm13)
Rs2
CS510 Computer Architectures
Lecture 5- 46
Vertical Micro-Instruction for RISC-S:
Data Path Control
• Output Bus - OUTBUS(OUT: 3 bits)
– MAR, MBR, PC, IR, R(Rd), Disable - needs to represent 6 kinds
OUT
INBUS2
000
Disable
INBUS1
001
MAR
OUTBUS
IR
010
MBR
OUTBUS
MAR
PC
Register
011
PC
OUTBUS
Memory
File
MBR
100
IR
OUTBUS
+4
101
Rd
OUTBUS
OUTBUS
110,111 Not used
ALU
Flag
• PC Control Field(P: 1 bit)
– PC increment, Disable increment - needs to represent 2 kinds
P
0
Disable
1
PC
PC + 4
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 47
Vertical Micro-Instruction for RISC-S:
Sequence Control
•
Branch set
Data Path Control
•
xx
00
01
10
11
xx
Next address
uPC(repeat)
uPC + 1
uPC + 2
uPC + 3
Branch set with condition codes
– Least significant m bits of address are replaced by the m conditions codes
Data Path Control
•
Cond
Branch Address
Cond
C-value
Complete conditional branch
Data Path Control
Branch Address
– If CC specified by Cond field is equal to the C-value, address specified in
the micro-instruction is the branch address
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 48
Vertical Micro-Instruction for RISC-S:
Sequence Control
•
Conditions in RISC-S
– CPU Flags: C, Z, S, O
– Machine language instruction OP-code field: T(t0t1t2) and F(f0f1f2f3)
•
Branch types: FLG(3 bits)
FLG
000
001
010
011
100
101
110,111
Not branching
Unconditional branch
Conditional branch on CPU flags(COND field in machine instruction)
Not used
Conditional branch on T flags
Conditional branch on F flags
Not used
• Conditional branch micro-instruction must specify Branch Type(FLG: 3
bits) and Values of the specified Flags(FVAL: 4 bits)
– Maximum number of flags to be tested against the values is 4(CPU
flags, F flags)
Data Path control
25
Control Unit Implementation
FLG FVAL
3
4
CS510 Computer Architectures
address
8
Lecture 5- 49
Vertical Micro-Instruction
for RISC-S
Vertical micro-instruction formats for RISC-S
0
1 2 3
4 5
6 7 8
9 10 11 12
14 15
17 18
M P AF LF S IN1 IN2 OUT FLG
21 22
FVAL
31
Branch Address
Data path control micro-instruction for RISC-S
0 1
0
2 3 4
M
5 6
7 8 9
10 11
12 13
15
P AF LF S IN1 IN2 OUT
Sequence control micro-instruction for RISC-S
0 1
34
7 8
1 FLG FVAL
Control Unit Implementation
15
Branch Address
CS510 Computer Architectures
Lecture 5- 50
Microprogram Model
FETCH
Routine
Instruction 1
Execution
Routine
Control Unit Implementation
Instruction 2
Execution
Routine
CS510 Computer Architectures
Instruction n
Execution
Routine
Lecture 5- 51
FETCH Routine
• Instruction Fetch
– Read Instruction from memory to store in IR
• Decode Instruction
– Separate instruction fields and store them in buffers
T
Rd
I(31-29), F
I(28-25), SC
I(24), COND
I(23-19), Ss1
I(18-14), Ss2
I(4-0), D
I(22-19),
I(12-0)
– Extend the displacement of the operand’s address into a 32-bit
displacement
S2
(I(12))19#D (sign extension)
– Fetch operands from registers
Rs1
Rs2
Control Unit Implementation
Reg[Ss1]
Reg[Ss2]
CS510 Computer Architectures
Lecture 5- 52
FETCH Routine
F
IR
MAR
PC, R
PC
PC + 4
MBR, Decode
T=0?
OP-code(I31-I25): T(t0t1t2), F(f0f1f2f3)
T: Instruction Type
F: Function Type
Instruction Decoding can be done either by hardware or microprogram.
We assume that decoding hardware does as follows;
n
y
T=5?
y
n
T=2?
y
n
T=3?
n
Illegal OP-code
Interrupt
y
FC
Control Unit Implementation
XF
SQ
IO
CS510 Computer Architectures
Lecture 5- 53
Execution Routine - Functional
FC
F=0?
n
F=1?
y
Rd
Rs1 + Rs2
Rd
n
y
F=4?
Rs1 - Rs2
Rd
n
y
F=5?
Rs1 ^ Rs2
n
y
F=8?
Rd
Rs1 v Rs2
y
Rd
shl Rs1
Illegal OP-code
F
Control Unit Implementation
n
CS510 Computer Architectures
Lecture 5- 54
Execution Routine - Transfer
XF
F=0?
n
y
n
F=1?
y
MAR
Rd
Rs1 + S2, R
MBR
MAR
MBR
Illegal
OP-code
Rs1 + S2, R
Rd
F
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 55
Execution Routine - Sequencing
SQ
F=1?
n
y
Rd
PC
F=0?
n
y
PC
Rs1 + S2
COND=1?
y
F=3?
n
Illegal
OP-code
y
n
PC
Rs1 + S2
F
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 56
Symbolic Microprogram
for RISC-S
FETCH:
FUN:
ADDR:
SUBR:
ANDR:
Rs1 v Rs2, goto FETCH;
shl Rs1, goto FETCH;
MAR
PC, R;
PC
PC + 4;
IR
MBR, decode;
if T=Func goto FUN;
if T=Trans goto XFR;
if T=Seq goto SEQ;
goto IO;
if F=ADD goto ADDR;
if F=SUB goto SUBR;
if F=AND goto ANDR;
if F=OR goto ORR;
if F=SLL goto SHFTR;
goto OTHERFUN;
ORR:
SHFTR:
Rd
Rd
XFR:
if F=LD goto LOAD;
if F=ST goto STORE;
goto OTHERXFR;
Rd
M[Rs1+S2], goto FETCH;
M[Rs1+S2]
Rd, goto FETCH;
Rd
Rd
Rd
JUMP:
Rs1 + Rs2, goto FETCH;
Rs1 - Rs2, goto FETCH;
Rs1 ^ Rs2, goto FETCH;
Control Unit Implementation
LOAD:
STORE:
SEQ:
if F=JMP goto JUMP;
if F=CALL goto CALL;
if F=RET goto RETURN;
goto OTHERSEQ;
if COND=true goto RETURN;
goto FETCH;
CALL:
Rd
PC;
RETURN: PC
Rs1 + S2, goto FETCH;
CS510 Computer Architectures
Lecture 5- 57
Decoding Micro-Instruction
in RISC-S
X
Y
Cc
A
C
DI
C0
Cm
Cr
Ri
Li
Ro
Lo
Logic
Unit
Adder
S
L
Shifter
PS
AN
AO
NS
LS
RS
SE
Z
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 58
Decoding Micro-Instruction
in RISC-S
AF field
AF=ADD
AF=SUB
AF=Pass
AF=Disa
A
1
1
0
0
C0
0
1
d
d
Cm
0
1
0
d
DI
0
0
1
d
Cc
0
0
0
0
Cr
0
0
0
0
AO
0
0
0
0
AN
d
d
d
d
PS
0
0
1
0
NS
1
1
1
d
LS
0
0
0
d
RS
0
0
0
d
SE
1
1
1
0
LF field
LF=OR
0
LF=AND 0
LF=Disa 0
LF=unusedd
d
d
d
d
d
d
d
d
d
d
d
d
0
0
0
d
0
0
0
d
1
1
0
0
0
1
0
d
0
0
0
d
1
1
1
d
0
0
0
d
0
0
0
d
1
1
1
d
S field
S=Disa
S=left
d
0
d
0
0
0
0
0
0
0
0
0
d
d
0
0
1
0
0
1
0
0
1
1
d
1
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 59
Horizontal Micro-Instruction
for RISC-S
Decoded form of control information in the micro-instruction
M0 M1 P C0 Cm A DI Cc Cr AN AO PS NS LS RS SE
2
1
1
1
1
1
1
1
1
1
FVAL
address
4
n
Control Unit Implementation
1
1
1
1
IN1
IN2
OUT
2
2
3
1
CS510 Computer Architectures
FLG
3
Lecture 5- 60
Microprogram Control Unit
• In-line execution
– We know it is simple if we have a uPC
• Repeat execution
– Disable incrementing uPC
• Conditional and Unconditional branch
– Target address or a part of the target address in the micro-instruction
– Branch conditions: CPU flags, Instruction’s T and F flags
• Loop
– We need a conditional branch and an iteration counter
– Loop counter(LCTR, and LZ flag that represents the state of LCTR, LZ
is set to 1 when LCTR represents 0
• Micro-routine call and return
– We know it is simple if we have a stack
– PUSH the return address when CALL, and POP for indirect branch
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 61
Redefining FLG Field
Definition of FLG field
FLG
Micro-instruction execution sequence
0000
In-line sequencing
0001
Unconditional branch
0010
Repeat
0011
Beginning of loop
0101
CALL
0110
RETURN
1000
Conditional branch on T
1001
Conditional branch on F
1100
Conditional branch on CPU flags
1101
Conditional branch on LZ flag
0100, 0111, 1010, 1011, 1110, 1111 are not used
Next micro-instruction
uPC
address
uPC
uPC
address
Stack
address
address
address
address
We need a address MUX at the
input of CSAR
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 62
Address MUX and
Loop Counter
SP
S0
S1
Stack
AMUX
uPC
LZ
=0
CSAR
PSH POP
+1
DPC
LCTR
Control Storage
AMUX Control
S0
0
0
1
1
S1
0
1
0
1
Address
Not used
uPC
address
stack
Micro-instruction
C
Control Unit Implementation
CS510 Computer Architectures
address
Lecture 5- 63
Decoding Flag Field
S1
CPU
FVAL
Z
S
C
O
Z 1 1 1
S 1 1 1
C 1 1 1
O 1 1 1
T0 T1 T2 1
F0 F1 F2 F3
LZ 1 1 1
S0
=
PSH
Compare
(0010+
0101)
1ddd
FMUX
0110
0000
En
DPC
0d1d
0d01
FLGD
0110
POP
FLG
Control Unit Implementation
FVAL
CS510 Computer Architectures
Lecture 5- 64
Advantages of
Microprogram
•
•
•
•
•
•
Flexibility and adaptability are high
Makes the development time shorter
Convenient for developing a computer family design
Easy to develop ICs
Maintenance and error detection/correction cost is lower
Development of Universal host
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 65
Disadvantages
of Microprogramming
• Inherently slow
• Not economic for a simple low cost machines
Control Unit Implementation
CS510 Computer Architectures
Lecture 5- 66