Transcript Document

7. Microarchitecture of Superscalars (5)
Dynamic Instruction Issue
Dezső Sima
Fall 2006
 D. Sima, 2006
Overview
•
1 The principle of dynamic instruction issue
•
2 Design space
•
2.1 Overview
•
2.2 Types of issue buffers
•
2.3 Operand fetch policies
•
3 Principle of operation of dynamic instruction issue
•
3.1 Dispatch bound operand fetching
•
3.2 Issue bound operand fetching
4 Implementation of dynamic instruction issue in superscalars
•
•
4.1 The introduction of dynamic instruction issue
•
4.2 Basic implementation schemes
5 Case examples
1. Principle of dynamic instruction issue (1)
Aim: • To eliminate the issue bottleneck of early (first generation)
supercalars
1. Principle of dynamic instruction issue (2)
The issue bottleneck
Icache
Cycles
I-buffer
Instr. window (3)
C
Dependent instructions
block instruction issue
EU
(a): Simplified structure of the mikroarchitecture assuming
unbuffered issue
i2
i3
i2
i6
i5
i1
C i+1
C
EU
i3
i
Issue
Decode,
check,
issue
Instr. window
i4
i+2
Executable inst ructions
Dependent inst ructions
Issue
(b): The issue process
Figure 1.1: The principle of dynamic instruction issue
1. Principle of dynamic instruction issue (3)
Eliminating the issue bottleneck
Dynamic instruction issue
I cache
(shelving, buffered issue)
I-buffer
Instr. window
Cycles
Instruct ion window
Decode/Issue
Dispatch
Instruct ions are dispatched without
checking for dependencies to the
shelving buffers (reservation stat ions)
C
i4
i3
i2
i1
i4
i3
i2
i1
i8
i7
i6
i5
i
C i+1
Shelving buffer
Issue
Shelving buffer
Dep. checking/
issue
Dep. checking/
issue
EU
EU
C
i+2
Shelved not dependent
instruct ions are issued
for execut ion to the EUs. Executable instructions
Dependent instructions
Issue
(a): Simplified structure of the mikroarchitecture assuming
buffered issue (shelving)
Figure 1.2: Principle of dynamic instruction issue
(b): The issue process
2. Design space of dynamic instruction issue
2.1 Overview
Dynamic instruction issue
Scope of dynamic
instr. issue
Layout of the issue
buffers
Types of
issue buffers
Operand
fetch policy
Instruction
issue scheme
2.2 Types of issue buffers
Types of issue buffers
Issue buffers
in the ROB
Reservation stations
(RS)
Individual
RSs
Central
RS
Group
RSs
RS
FX
RS
RS
RS
FX
EU
FP
EU
Power1 (1990)
PowerPC 603 (1993)
PowerPC 604 (1995)
Power4 (2001)
Power5 (2004)
K5 (1995)
K7 (1999), K8 (2003)
FX
EU
FP
RS
FX
EU
FX
EU
ES/9000 (1992)
Power2 (1993)
R10000 (1996)
PM1(Sparc64)(1995)
Alpha 21264 (1997)
FX
EU
FX
EU
FP
EU
Pentium Pro (1995)
Pentium II (1997)
Pentium III (1999)
Pentium IV (2000)
Pentium M (2003)
Core (2006)
FX
EU
FP
EU
Lightning (1991)p
K6 (1997)
Dynamic instruction issue
Scope of buffered
issue
Layout of the issue
buffers
Types of
issue buffers
Operand
fetch policy
Instruction
issue scheme
2.3 Operand fetch policies
Operand fetch policies
Issue bound
operand fetch policy
Dispatch bound
operand fetch policy
I-buffer
I-buffer
Decode / Issue
Decode / Issue
Source reg. identifiers
Dispatch
Reg. file
Issue
Opcodes, destination reg. identifiers
Source 2 operands
Issue
Op2/Rs2
IB
Opcodes, destination
reg. identifiers
IB
OC Rd Op1/Rs1
IB
OC Rd Rs1 Rs2
OC Rd Rs1 Rs2
Source reg. identifiers
Source 1 operands
IB
Source reg. identifiers
Dispatch
OC Rd Op1/Rs1
Reg. file
Source 1 operands
Op2/Rs2
Source 2 operands
EU
Rd, result
EU
EU
Figure 2.1: Operand fetch policies
EU
3 Principle of operation of dynamic instruction issue
3.1 Dispatch bound operand fetching (1)
• Checking the availability of operands
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch
V
Reg. file
Opcodes, destination reg. identifiers
Source 1 operands
Source 2 operands
V
V
IB
Issue
V
IB
OC Rd Op1/Rs1
EU
Rd, result
V
Op2/Rs2
OC Rd Op1/Rs1
EU
Op2/Rs2
3.1 Dispatch bound operand fetching (2)
• Updating the issue buffers
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch
V
Reg. file
Opcodes, destination reg. identifiers
Source 1 operands
Source 2 operands
V
V
IB
Issue
V
IB
OC Rd Op1/Rs1
EU
Rd, result
V
Op2/Rs2
OC Rd Op1/Rs1
EU
Op2/Rs2
3.2 Issue bound operand fetching
Checking the availability of operands
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch
Issue
IB
IB
OC Rd Rs1 Rs2
OC Rd Rs1 Rs2
Source reg. identifiers
V
Opcodes, destination
reg. identifiers
Reg. file
Source 1 operands
Source 2 operands
EU
EU
4. Implementation of dynamic instruction issue in superscalars
4.1 The introduction of dynamic instruction issue
RISC processors

DEC
Motorola
MC 88000
HP
PA
IBM
Power
PowerPC
Alliance
PowerPC
Alpha 21064 (2)
Alpha 21064A (2)
Alpha 21264 (4)
MC 88110 (2)
PA7100 (2)
Power1 (4)
(RS/6000)
PA7200 (2)
PA8000 (4)
PA 8200 (4)
R 10000 (4)
R 12000 (4)
Power2 (4)
RSC (4)
2
MIPS
Alpha 21164 (4)
PPC 601 (3)
2
PPC 604 (4)
2
PPC 603 (3)
R
PPC 620 (4)
PPC 602 (2)
2
2
R 8000 (4)
UltraSparc (4)
Sun/Hal
SuperSparc (3)
SPARC
PM1 (4)
(Sparc64)
CISC processors
Intel
80x86
IBM
ES
TRON
Gmicro
CYRIX
M1
Motorola
Pentium (2)
ES/9000 (2)
Gmicro/500 (2)
M1 (2)
MC 68000
AMD
K5
NexGen
Nx
PentiumPro (~2)
MC 68060 (3)
K5 (~2)
Nx586 (1/3) 1
1989
1990
1991
1992
1993
1
CISC processors
- Partial dynamic issue
- Full dynamic issue
2
1994
1995
1996
The Nx586 has scalar issue for CISC instructions but a 3-way superscalar
superscalar core for converted RISC instructions.
PowerPC is abbreviated here to PPC
Figure 4.1: The introduction of dynamic instruction issue
1997
4.2 Basic implementation schemes
Operand fetch policy
Types of issue buffers
Basic issue buffer schemes
Issue buffers
in the ROB
Reservation stations
(RS)
Individual
RSs
Dispatch
bound
Issue
bound
PowerPC 603 (1993)
PowerPC 604 (1995)
K5 (1995)
Power1 (1990)
Power4 (2001)
Power5 (2004)
Nx586 (1994)
K7 (1999), K8 (2003)
Central
RS
Group
RSs
Dispatch
bound
PM1(Sparc64)
(1995)
Issue
bound
Dispatch
bound
Issue
bound
Dispatch
bound
Issue
bound
Pentium Pro (1995)
Pentium II (1997)
Pentium III (1999)
ES/9000 (1992)
Power2 (1993)
R10000 (1996)
Alpha 21264 (1997)
Pentium IV (2000)
Pentium M (2003)
Core (2006)
Lightning (1991)p
K6 (1997)
5. Case example (1)
Individual issue buffers
Figure 5.1: The microarchitecture of the Athlon
5. Case example (1)
Individual issue buffers (2)
Decoders
Issue buffers
EUs
Figure 5.2: Integer issue buffers of the K8L
Source: Malich, Y.„AMD's Next Generation Microarchitecture Preview: from K8 to K8L”, Aug. 2006.
5. Case example (2)
Group issue buffers
Figure 5.3: The microarchitecture of the Alpha 21264
Source: Kessler, R.E. et al. .„The Alpha 21264 Microprocessor Architecture”, h18002.www1.hp.com/alphaserver
5. Case example (3)
Central reservation station (1)
Figure 5.3: The microarchitecture of the Core processor
Source: Kanter, D., „Intel’s next Generation Microarchitecture Unveiled”, Real World Tech., 2006 March 9.