Transcript Slide 1
Application of the DRS Chip for Fast Waveform Digitizing Stefan Ritt Paul Scherrer Institute, Switzerland Question ? 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ March 14th, 2009 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ USB Power TIPP09 Tsukuba 2 Switched Capacitor Array 0.2-2 ns Inverter “Domino” ring chain IN Waveform stored Clock Shift Register Out FADC 33 MHz “Time stretcher” GHz MHz March 14th, 2009 TIPP09 Tsukuba 3 Switched Capacitor Array • Cons Dt Dt Dt Dt Dt • No continuous acquisition • Limited sampling depth • Nonlinear timing • Pros • High speed (6 GHz) high resolution (11.5 bit resol.) • High channel density (9 channels on 5x5 mm2) • Low power (10-40 mW / channel) • Low cost (~ 10$ / channel) March 14th, 2009 TIPP09 Tsukuba 4 DRS4 • Differential inputs, differential outputs • Sampling speed 500 MHz … 6 GHz, PLL stabilized • Readout speed 30 MHz, multiplexed or in parallel March 14th, 2009 PLL WSRIN DENABLE DWRITE REFCLK IN0 DTAP A0 A1 A2 A3 LVDS DOMINO WAVE CIRCUIT MUX CHANNEL 0 OUT0 CHANNEL 1 OUT1 CHANNEL 2 OUT2 CHANNEL 3 OUT3 CHANNEL 4 OUT4 CHANNEL 5 OUT5 CHANNEL 6 OUT6 IN7 CHANNEL 7 OUT7 IN8 CHANNEL 8 IN1 IN2 IN3 IN4 IN5 IN6 WRITE CONFIG REGISTER • 8+1 ch. each 1024 cells AGND AVDD DSPEED PLLOUT PLLLCK ENABLE • UMC 0.25 mm 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard FUNCTIONAL BLOCK DIAGRAM WRITE SHIFT REGISTER • Designed for the MEG experiment at PSI, Switzerland WSROUT STOP SHIFT REGISTER RSRLOAD SRIN SRCLK READ SHIFT REGISTER MUX OUT8/ MUXOUT O-OFS BIAS ROFS SROUT RESET CONFIG REGISTER DVDD DGND TIPP09 Tsukuba 5 How to minimize dead time ? • Fast analog readout: 30 ns / sample • Parallel readout • Region-of-interest readout AGND AVDD DSPEED PLLOUT PLLLCK PLL WSRIN DENABLE DWRITE REFCLK LVDS DOMINO WAVE CIRCUIT IN0 DTAP A0 A1 A2 A3 MUX ENABLE • Simultaneous write / read FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 OUT1 CHANNEL 2 OUT2 CHANNEL 3 OUT3 CHANNEL 4 OUT4 CHANNEL 5 OUT5 CHANNEL 6 OUT6 IN7 CHANNEL 7 OUT7 IN8 CHANNEL 8 IN1 IN2 IN3 IN4 IN5 IN6 WRITE SHIFT REGISTER OUT0 WRITE CONFIG REGISTER CHANNEL 0 WSROUT STOP SHIFT REGISTER RSRLOAD SRIN SRCLK READ SHIFT REGISTER MUX AD9222 12 bit 8 channels OUT8/ MUXOUT O-OFS BIAS ROFS SROUT RESET CONFIG REGISTER DVDD DGND March 14th, 2009 TIPP09 Tsukuba 6 ROI readout mode delayed trigger normal stop trigger stop after latency Trigger Delay stop 33 MHz e.g. 100 samples @ 33 MHz 3 us dead time 300,000 events / sec. March 14th, 2009 readout shift register Patent pending! TIPP09 Tsukuba 7 Daisy-chaining of channels Domino Wave clock Domino Wave clock 1 enable input Channel 0 0 enable input Channel 0 0 enable input Channel 1 1 enable input Channel 1 1 Channel 2 0 Channel 2 0 Channel 3 1 Channel 3 1 Channel 4 0 Channel 4 0 Channel 5 1 Channel 5 1 Channel 6 0 Channel 6 0 Channel 7 1 Channel 7 DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth March 14th, 2009 TIPP09 Tsukuba 8 Simultaneous Write/Read FPGA 0 1 Channel 0 0 1 Channel 1 1 0 Channel 2 0 Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 readout 8-fold analog multi-event buffer Expected crosstalk ~few mV March 14th, 2009 TIPP09 Tsukuba 9 Trigger an DAQ on same board DRS4 trigger DRS MUX • DRS readout (6 GHz samples) though same 8-channel FADCs analog front end • FPGA can make local trigger (or global one) and stop DRS upon a trigger FADC 12 bit 65 MHz FPGA global trigger bus • Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS LVDS SRAM “Free” local trigger capability without additional hardware March 14th, 2009 TIPP09 Tsukuba 10 DRS4 Performance Test Results Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) QFP package final bus width 850 MHz (-3dB) Simulation Measurement March 14th, 2009 TIPP09 Tsukuba 12 Timing jitter • Inverter chain has transistor variations Dti between samples differ “Fixed pattern aperture jitter” • “Differential temporal nonlinearity” TDi= Dti – Dtnominal • “Integral temporal nonlinearity” TIi = SDti – iDtnominal • “Random aperture jitter” = variation of Dti between measurements Dt1 Dt2 Dt3 Dt4 Dt5 TD1 March 14th, 2009 TI5 TIPP09 Tsukuba 13 Fixed jitter calibration • Fixed jitter is constant over time, can be measured and corrected for • Several methods are commonly used • Most use sine wave with random phase and correct for TDi on a statistical basis March 14th, 2009 TIPP09 Tsukuba 14 Sine Curve Fit Method i 500 1024 ( y ji (a j sin(i 2 j 0 i 0 2 j i ) o j ))2 min fj yji : i-th sample of measurement j aj fj j oj : sine wave parameters i : phase error fixed jitter “Iterative global fit”: • Determine rough sine wave parameters for each measurement by fit • Determine i using all measurements where sample “i” is near zero crossing • Make several iterations j March 14th, 2009 S. Lehner, B. Keil, PSI TIPP09 Tsukuba 15 Fixed Pattern Jitter Results • TDi typically ~50 ps RMS @ 5 GHz • TIi goes up to ~600 ps • Jitter is mostly constant over time, measured and corrected • Residual random jitter 3-4 ps RMS March 14th, 2009 TIPP09 Tsukuba 16 Applications of the DRS4 Chip What can we do with this technology? Flash ADC Technique PMT/APD Wire Q-sensitive Preamplifier Baseline Shaper Restoration PMT/APD Transimpedance Preamplifier Wire FADC 60 MHz 12 bit Amplitude TDC Time FADC 5 GHz 12 bit • • • • Digital Processing Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is fast enough All operations (CFD, optimal filtering, integration) can be done digitally March 14th, 2009 TIPP09 Tsukuba 18 How to measure best timing? Simulation of MCP with realistic noise and different discriminators J.-F. Genat et al., arXiv:0810.5590 (2008) March 14th, 2009 TIPP09 Tsukuba 19 On-line waveform display S848 PMTs “virtual oscilloscope” template fit click pedestal histo March 14th, 2009 TIPP09 Tsukuba 20 Pulse shape discrimination Example: /g source in liquid xenon detector (or: g/p in air shower) g (t t 0 ) /τ s (t t 0 )/τ d (t t 0 ) /τi V(t) A e Be Ce θ(t t 0 ) [...]θ.. t 0 t r ) Leading edge March 14th, 2009 Decay time AC-coupling TIPP09 Tsukuba Reflections 21 t-distribution t = 21 ns tg = 34 ns Waveforms can be clearly distinguished g March 14th, 2009 TIPP09 Tsukuba 22 Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” Experiment 500 MHz sampling • Find hit in waveform • Shift (“TDC”) and scale (“ADC”) template to hit • Minimize 2 • Compare fit with waveform • Repeat if above threshold • Store ADC & TDC values Pile-up can be detected if two hits are separated in time by ~rise time of signal March 14th, 2009 TIPP09 Tsukuba 23 Timing Big Systems I LMK03000 Clock Conditioner (National Semiconductor) Jitter: 400 fs Global Clock ~20 MHz Reference Clock for DRS4 PLL 2.5 MHz Reference Clock for timing channel March 14th, 2009 TIPP09 Tsukuba 24 Timing Big Systems II Experiment wide global clock LMK03000 PLL Domino Wave DRS4 Chip Channel 0 Channel 1 • Global clock locks all Domino Waves to same frequency and phase Channel 2 Channel 3 Channel 4 Channel 5 • Residual random jitter: 25 ps Channel 6 • Even better timing can be obtained by clock sampling Channel 8 Channel 7 • MEG Experiment: Single LVDS clock distributed over 9 VME crates March 14th, 2009 TIPP09 Tsukuba 25 Experiments using DRS chip MEG 3000 channels DRS2 upgraded to DRS4 soon MAGIC-II 400 channels DRS2 BPM for XFEL@PSI 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned) March 14th, 2009 TIPP09 Tsukuba PET 26 Availability • DRS4 can be obtained from PSI on a “non-profit” basis • Delivery “as-is” • Costs ~ 10-15 USD/channel (1000-1500 JPY) • USB Evaluation board as reference design • VME boards from industry in 2009 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz March 14th, 2009 TIPP09 Tsukuba 27 Conclusions • Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future • DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 4 ps timing resolution • ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology http://drs.web.psi.ch March 14th, 2009 TIPP09 Tsukuba 28 Datasheet http://drs.web.psi.ch/datasheets March 14th, 2009 TIPP09 Tsukuba 30 Signal-to-noise ratio (DRS3!) 0.52 SNR: Crosstalk from trigger signal ANALOG OUTPUT [V] “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA 0.51 0.5 0.49 1 V linear range / 0.35 mV = 69 dB (11.5 bits) 0.48 200 200 180 180 140 120 100 80 80 40 20 20 March 14th, 2009 0.51 0 0.48 0.52 TIPP09 Tsukuba 1000 100 40 0.5 OUTPUT VOLTAGE [V] 800 120 60 0.49 400 600 BIN NUMBER 140 60 0 0.48 200 160 OCCURENCE Offset Correction 160 OCCURENCE 0 0.49 0.5 OUTPUT VOLTAGE [V] 0.51 0.52 31 Interleaved sampling delays (167ps/8 = 21ps) 6 GSPS * 8 = 48 GSPS G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) Possible with DRS4 if delay is implemented on PCB March 14th, 2009 TIPP09 Tsukuba 32 Constant Fraction Discr. Delayed signal Inverted signal Sum + S Latch + Latch Latch Latch Latch 12 bit Latch Clock <0 0 MULT March 14th, 2009 & TIPP09 Tsukuba 33