Transcript PEBS- Electronics

PEBS Electronics
W. Karpinski
I. Physikalisches Institut
Aachen, 10 January 2007
5 Feb 2007
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Outline
An overview of the PEBS Electronics
Subdetector Readout:
- TRD
- Tracker
- ECAL
- ToF
- TGB (Trigger Box)
Summary
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PEBS Electronics
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AMS Electronics
M
U
X
Detector
ADC
Sequence
Trigger Input
(H )V D etect.
V dd (A nalog)
DSP
Gate
Array
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S ubd.
P ower
AMSWire
CDDC
DSP
GA
Command Distrib, Data Collect.
CDDC
MAIN HRDL
DATA LRDL
Comp
Mem
Gate
Busy
Trigger
Memories
LRS
V dd(D igital)
Lin
Reg
DC-DC Converters
(28 -> 5,3.3,+-2)
(High Efficiency)
Data
Reduction
AmsW
Custom
ASIC
CDP: Common
Digital
Part
Sample
& Hold
Digitization
Global DAQ
AmsW
Subdetector DAQ
2x CAN
S lave M&C
28 V
Global
P ower
120V
M .Ca p e l l J a n 0 4
28V Filter (I/O)
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PEBS -TRD
• 16 layers, 7 chambers/layer =112
chambers
• 16 “straw tubes” per chamber
• 1792 channels in total
• the readout schema could be the same
as in AMS2
• the available spare boards can be used
in PEBS-TRD readout
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AMS2-TRD Readout
UFE
= front end
UTE
= tube end
UHVD = high voltage distribution
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UPSFE
UDR
JINF
UHVG
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= power supply for UFE
= data reduction board
= interface board for higher DAQ
= high voltage generator
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AMS2-TRD Readout
UPD
U-Crate
UDR2
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UPSFE
JINF
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UHVG
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Front-End Electronics : UFE
Airborn Connectors
MA231-032-125-5000
Schematic Diagram of UFE
ESD-Protection
IC and Network
Ch 1 - 32
+2.0 A
Micro D-Sub
Connector 21 pol.
+2.0 A
-2.0 A
GND
+2.0 D
-2.0 D
-2.0 A
VA 1
+2.0 D

V
DC shift
+2.0 D
-2.0 D
118mm
VA 2
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+
-
SDATA+
SDATA-
-2.0 D
SCLK+
+
Ch 33 - 64
65.8mm
12 bit ADC
AD7476
-
SCLK-
CAL
Dreset1, Dreset6, ShiN1, ShiN2,
CLK_FF, Dreset5, hold, hold_b, test_on
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Hybrid Control Circuit
& Logic Unit
S
SB
H
HB
8
Data Reduction UDR2
Gate
Array
Hot Side
DSP
Cold Side
OUT
Analog::Digital
Isolation Barrier
Digitized Data
7x 64x IN
Performs:
• buffering of the raw data
• data reduction in the DSP
• data transmission to the Global DAQ
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Structure of the PEBS -TRD Readout
Equipment needed:
28x UFE, 4x UDR, 2x UPSF, 4xUHVD, 1x C&DI
TRD Power Consumption = UFE(7W) + Ucrate(13W) + UPD(11W) =31W
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PEBS -TRD CRATE
UDR -data reduction board
UPSFE -power supply for UFE
C&DI - interface for higer DAQ
UHVD - high voltage generator
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PEBS -Tracker
• 4 disks á 46 modules = 184 Modules
• readout using SiPM arrays with 32 strips
• 4 SiPM arrays on each module end
 two Front End Hybrids/module á 128 channels
• in total 47104 channels
arrangement of the SiPM arrays on the module end
SiPM array with 16 channels
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PEBS -Tracker
• SiPM specifications
- channel size: 1 mm x 0.25 mm
- pixel size: 0.043 x 0.043 mm2
= 135 pixels/channel  8 bit ADC
- operating voltage: ~ 40V
- gain = 0.8 x 106  preamplifier with large dynamic range necessary
- SiPM gain varies with bias voltage: 40% / 1V
Do we need gain adjustment for individual channels ?
If yes, it must be implemented on chip level (DAC)
 new chip design necessary
 significant increase of cost and development time
- dark current =500 nA/channel
- dark count ~ .5 MHz (40V, T=22°C)
 fast shaping time required to reduce pile up
 ac coupling between detector and preamplifier
or active leakage current compensation on the chip
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SiPM- Behaviour
Temperature depandance from Nakamura (KOBE)
(7th ACFA workshop on Physics and Detector at the Linear Collider)
• gain shift by 1.5% /°C
• gain variations with bias voltage by 80%/1V
• increase of noise rate by factor of 70%/10°C
 the operation temperature of SiPM should be well controlled
the operation temperature should be low
 precise voltage control for good gain stability
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ROCs possibly adequate for SiPM signal processing
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MAROC : 64 ch MAPMT chip for ATLAS lumi
•
•
Characteristics
64 PMT channels input (50-100 Ω)
Variable gain current conveyor (0-2)
6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16
64 discriminator outputs (GTL)
100% sensitivity to 1/3 photoelectron
(50fC). Counting rate up to 2 MHz
Common threshold loaded by internal
10bit DAC
1 multiplexed charge output with
variable shaping 20-200ns and Track &
Hold.
Dynamic range : 11 bits (2fC - 5 pC)
Crosstalk < 1%
©N. Seguin (LAL)
Hold signal
64 PM
inputs
Variable
Slow
Shaper
Variab
le
Gain
Pream
p.
Multiplexed
charge output
S&H
Bipolar
Fast Shaper
64Trigger
outputs
10 bit DAC
Gain correction
6 bits/channel
discriminator
threshold
10 bits DAC
Synoptic diagramm of MAROC1
Technology : AMS SiGe 0.35µm
Submitted 13 june 05 Area 12 mm2
Dissipation 130 mW @ VDD=3.5V
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ILC SiPM Chip
•
•
•
•
•
•
•
18-channel 8-bit DAC (0-5V)
18-channel front-end readout :
Variable gain charge preamplifier (0.67 to 10
V/pC)
Variable shaping time CRRC2 shaper (12 to 180
ns)
Track and hold  1 multiplexed output
Power consumption : ~200mW (supply : 0-5V)
Technology : AMS 0.8 m CMOS
Chip area : ~10mm²
Package : QFP-100
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Channel architecture for SiPM readout
40kΩ
100MΩ
0.1pF
8-bit
ASIC
0.2pF
1.2pF
DAC
0.4pF
0.6pF
0-5V
0.8pF
0.3pF
in
12kΩ
4kΩ
50Ω
2.4pF
10pF
Rin =
10kΩ
8pF
4pF
2pF
24pF
12pF
1pF
100nF
6pF
3pF
Charge Preamplifier :
Low noise : 1300e- @40ns
Variable gain :
4bits : 0.67 to 10 V/pC
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CR-RC² Shaper :
Variable time constant : 4 bits (12 to 180ns)
12ns  photoelectron measurement (calibration mode)
180ns  Mip measurement (physics mode)
compatibility with ECAL read-out
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Prospective for A-HCAL SiPM Chip
•
Similar developments for AHCAL
Chip fully dedicated to SiPMs
Internal DAC for SiPM gain adjustment (5V range)
Auto-trigger (fast shaper + Discriminator)
Internal TDC, 1 ns step
Internal 12 bit ADC
Power pulsing
8 bit DAC
(0-5V)
T&H Analogue
Memory
Charge
Ouput
…
Shaper tp~30-40ns
12-bit
ADC
x1
Auto-trigger
in
Variable gain
Preamplifier
Capacitance
for AC
coupling
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TDC
Fast Shaper
Threshold
Discri
12-bit DAC
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Time
Ouput
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PEBS-Tracker Readout
FE-Hybrid Ver.2
• FE Hybrid consists of:
- biasing network
- 2 VA64 chips
- 1 amplifier
- readout control
- expected power consumption
2 mW / channel
- readout time ~85 µs/event
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Tracker Front-End Hybrid
SiPMs Arrays
VA64-chip
Biasing & AC coupling
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Data Reduction TDR2 Boards
Analog
Receivers
DSP
+80V
• 6 analogue inputs and 6 ADCs
per board
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OUT
Gate
Array
ADC
Analog::Digital
Isolation Barrier
2x ADC
384x IN
• Architecture
- on FE-Hybrid analog signal
processing only
- TRD2 performs digitization
calibration and data reduction
for 2048 channels
640x IN
• The readout of PEBS-Tracker can
be realized using modified TRD2
boards from AMS
TDR2
Data Reduction
Data Compresion
PEBS-Tracker Readout
• 16 FE-Hybrids á 128 channels connected to 1 TDR =2048 channels/TDR
• 368 FEHs, 23 TDRs and 2 crates á 12 TRDs necessary for Tracker readout
Power consumption: 85W on FEHs +94W in TDRs +47W in PSs = 226W
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PEBS-Tracker Crate
TDR -data reduction board
TPSFE -power supply for Front End
C&DI - interface for higer DAQ
TBIAS - bias voltage generator
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PEBS ECAL Electronics
• 80 Layers, 95 modules/layer
• Two modules will be readout by one SiPM  3800 channels in total
• Readout using SiPMs with the size 3mm x 3mm, ~8100 pixels / SiPM
• The same readout architecture as for the PEBS-Tracker
• Could be the same ASIC (VA64-SiPM)
3 mm
3 mm
SiPM
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PEBS ECAL Electronics
• Front-End Board with 6 VA64-SiPM chips
• One board collects the signals from one side of 2 super layers = 384 channels
• 5 Front-End Boards controlled by 1 modified TRD board = 1920 channels/TDR
Power consumption: 7 W on FEHs +8 W in TDRs + 4 W in PSs = 19 W
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PEBS-ECAL Crate
EPSFE -power supply for Front End
EBIAS - bias voltage generator
TDR
-data reduction board
C&DI
- interface for higer DAQ
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Scintillator Electronics
•
•
4 ToF planes á 8 scintillator paddles
32 scintillators in total with
-
(4 SiPMs ) per end  256 channels or
- one PM per end  64 PMs in total
Provides:
•
fast (~30ns) coincidence between at least 3 out of
4 ToF planes to select particles within the main
PEBS acceptance
•
measurement of the particle velocity including the
direction of the particle, (resolution of 100ps)
•
measurement of the absolute charge of particles
•
rejection of protons with E<1GeV at the trigger
level
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PM vs SiPM
High Voltage (2000V)
Low voltage (30V-60V)
Influenced by magnetic fields
Tested up to 4 Tesla
Influenced by vibrations
Not influenced by vibrations
Fragile and heavy
Light and robust
Low noise
High noise
Good temperature stability
Sensitive to temperature variation
Better gain stability
Gain sensitive to voltage variation
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AMS2 Scintillator Electronics
TOF Readout in AMS2 for 24 PMTs (20 ToF and 4 ACC ) consists of:
- SDR2: data collection and reduction & slow control
- 4 x SFET2: charge and time measurement of TOF anodes (5 PMs/ board)
- SFEA2: charge and time of ACC
- SFEC: dynode charge
- SPT2: pre-trigger unit
fast trigger input
- TSPD: DC/DC converters
- SHV: high voltage box
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PM-PEBS Scintillator Electronics
TOF Readout in PEBS for 64 PMTs will consist
of three crates:
- 1 x SDR2: data collection and reduction
& slow control
- 5 x SFET2: charge and time measurement
TOF anodes (5 PMs/ board)
- 1 x SPT2: pre-trigger unit, fast trigger input
- 3 x SHV boxes: high voltage generator
- 3 x TSPD: DC/DC converters
SHV-Box
TSPD
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Potential ROCs for ToF with SiPms
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ASIC production for OPERA target tracker
• Readout ASIC for multi-anode
Photomultiplier (Hamamatsu)
OPERA_ROC (2002)
32 channels
Variable gain preamp
Autotrigger on ¼ p.e.
BiCMOS 0.8µ
3 000 chips
64 ch front-end board (BERN)
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(S. Blin, T. Caceres, CdLT, G. Martin, L. Raux)
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MAROC : 64 ch MAPMT chip for ATLAS lumi
•
•
Characteristics
64 PMT channels input (50-100 Ω)
Variable gain current conveyor (0-2)
6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16
64 discriminator outputs (GTL)
100% sensitivity to 1/3 photoelectron
(50fC). Counting rate up to 2 MHz
Common threshold loaded by internal
10bit DAC
1 multiplexed charge output with
variable shaping 20-200ns and Track &
Hold.
Dynamic range : 11 bits (2fC - 5 pC)
Crosstalk < 1%
©N. Seguin (LAL)
Hold signal
64 PM
inputs
Variable
Slow
Shaper
Variab
le
Gain
Pream
p.
Multiplexed
charge output
S&H
Bipolar
Fast Shaper
64Trigger
outputs
10 bit DAC
Gain correction
6 bits/channel
discriminator
threshold
10 bits DAC
Synoptic diagramm of MAROC1
Technology : AMS SiGe 0.35µm
Submitted 13 june 05 Area 12 mm2
Dissipation 130 mW @ VDD=3.5V
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Next version – MAROC2
Hold signal
Variable
Slow Shaper
20-100 ns
Photons
64 inputs
Photomultiplier
64 channels
Variable
Gain
Preamp.
Gain correction
64*6bits
3 discri
thresholds
(3*12 bits)
•
•
New features: •
•
•
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Multiplexed
Analog charge output
S&H
S&H
Bipolar
Fast Shaper
64
Wilkinson
12 bit ADC
80 MHz
encoder
Unipolar
Fast Shaper
Multiplexed
Digital charge output
64 trigger outputs
3 DACs
12 bits
LUCID
Substrate separation
Unipolar fast shaper
3 discriminators
80MHz encoding
12bits Wilkinson ADC
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SPIROC for AHCAL SiPM
• Si PM Integrated Read Out Chip (Mar 07)
Chip fully dedicated to SiPMs developped after ECAL chip
Internal DAC for SiPM gain adjustment (5V range)
Auto-trigger (fast shaper + Discriminator)
Internal TDC, 1 ns step
Internal 12 bit ADC
Power pulsing
8 bit DAC
(0-5V)
T&H Analogue
Memory
Charge
Ouput
…
Shaper tp~30-40ns
12-bit
ADC
x1
Auto-trigger
in
Variable gain
Preamplifier
Capacitance
for AC
coupling
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TDC
Fast Shaper
Threshold
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Discri
12-bit DAC
Time
Ouput
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SiPM-PEBS-TOF Crate
C&DI
SDR
SFE
SPT
SPSFE
SBIAS
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- interface for higer DAQ
- data reduction board
- charge and time measurement
- pre-trigger
- voltage supply for Front End
- bias generator for SIPM
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PEBS Trigger Electronics
•generates Fast Trigger: 50-70 ns after the hit based on a coincidence between at
least 3 out of 4 ToF planes
•evaluates signals from ToF and ECAL
• if any of predeterminated patterns of these signals occurs generates
Level-1 trigger 1µs after the hit
•starts digitization and data flow for all subdetectors
•controls the BUSY signal to ensure that the event is collected from the complete
detector
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PEBS-Trigger Crate
TLV1
TTBX
JINJ
5 Feb 2007
- level 1 trigger
- fast trigger, fast in/out and logic
- intermediate DAQ, 1CDDC,
24 links to sleeves
4 links to masters
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Summary
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Summary
Power Consumption (ToF readout with PMs)
Channels
Power FE
[W]
Power DAQ
[W]
Power PS
[W]
Power Total
[W]
TRD
1792
7
13
11
31
Tracker
47104
94
94
47
236
ECAL
3800
8
8
4
19
64
11
68
32
112
Subsystem
TOF
Trigger
Slow Control
5
2
1
3
Main DAQ
45
PDS
60
Contingency
100

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Summary
• TRD Readout boards used in AMS02 can be utilized without any changes
for PEBS-TRD readout
• For Tracker and ECAL Front End new developments are necessary:
 investigation of adequate readout chip
 Front-End Hybrids
 modifications of voltage supply boards for front end
 new design of bias voltage generator boards
 new backplanes
• Readout Architecture of TRD2 boards can be applied in PEBS Tracker
and ECAL but the design of the readout boards must be slightly modified
to much the detector granularity
• Two version of TOF electronics possible:
 readout using PMs; AMS2 TOF electronics can be easily adapted to
PEBS needs
readout using SiPMs; new designs necessary
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Summary
• Expected total power dissipation amounts to ~ 600 W, including 100 W
contingency
• Interfaces for power and interface for data transfer to Earth must be
investigated
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