Transcript Introduction of Real-Time Embedded System Design

hArtes hArtes Overview
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Holistic Approach to
Reconfigurable real Time
Embedded Systems
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What’s hArtes?
hArtes: FP6 applied research integrated project (IP)
Started on 01 Sept 2006  currently in specification
development phase
17.3 M€ cost, 10.15 M€ funding
61% industry, 39% university
3 years duration140 person month
14 Partners, 5 Nations
6 Universities, 6 Companies, 2 Research Centers
hArtes web site: www.hartes.org (under construction)
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hArtes objectives
Develop a toolchain and a methodology supporting
effective automatic or semi-automatic design of
complex heterogeneous embedded systems.
Design a scalable heterogeneous and reconfigurable
hardware platform that can be re-targeted to produce
optimized real-time embedded systems.
Validate the tool chain on a set of innovative
applications in the audio and video field
“To develop the next generation of technologies, methods and tools for modelling, design, and
implementation and operation of hardware/software systems embedded in intelligent
devices. An end-to-end systems vision should allow building cost-efficient ambient intelligence
systems with optimal performance, high confidence, reduced time to market and faster
deployment.”
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hArtes: holistic vision
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ALGORITHMs
OEM
Fraunhofer IGD
Uni P. Marche
Uni d’Avignon
Thales
Faital
Thomson
Strong Industrial / Academic Collaboration to
develop tool chain for heterogeneous
reconfigurable multichip platforms
TOOLs
TU Delft
Poli Milano
Imperial College
Inria
Uni Ferrara
SOLUTIONs
Atmel
Leaff
Scaleo Chip
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Reduce time spent dealing with implementation details
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Objectives of the tool chain
Holistic approach:
Fill the gap between algorithms, architectures,
integration and test groups
Facilitate the management of the entire flow, to allow
identifying optimisation opportunities hidden in
different parts of the design
Reduced time to market.
Start from high level application description using
graphical entry, domain specific languages or C
Support the automatic system implementation
System flexibility through:
Reconfigurability
Easier design space exploration to identify the best
system solution: from feasibility to optimality
Manage product variants
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hArtes tool chain top level flow
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Tool chain details
Annotated C
Annotations
C2C
TUD
Annotated C
Profiling
TUD
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TaskPartitioning
Polimi
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TasksTransformation
Imperial
Annotated C
DataRepresentation
Imperial
Annotated C
DecisionMapping
Imperial
Annotated C
CodeGeneration
Generic GPP
(C+macros)
GPP
Molen code
GPP comp
Molen
ELF obj
ELF obj
Linker
Imperial
DSP
C code
FPGA
DSP comp
C2VHDL
ELF obj
Bitstream
TUD
Executable code (ELF)
- Loader
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Atmel+TUD
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Performance improvement in hArtes
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hArtes toolchain innovation
Innovations of the hArtes tool chain include:
a framework that allows implementing novel
algorithms for design space exploration, supports
design partitioning automation, task transformation,
choice of data representation, and metric evaluation
for HW and SW components;
a system synthesis tool producing near optimal
implementations that best exploits the capability of
each type of processing element; dynamic HW
reconfigurability can be exploited to support system
upgrade or adaptation to operating conditions;
diagrammatic and textual formats in algorithm
description and exploration.
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hArtes applications
Standard and Legacy applications AND innovative
applications for:
In car / home / office speech and audio
enhancement
Wavefield synthesis for audio applications
Audio surveillance and control
Video applications
Allowing:
Testing and validation of the tool chain on
complex use cases
Demonstration of the achievements
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hArtes Applications
ACIS = Advanced Car Information System.
Includes advanced audio, speech processing
enhancement and speech / speaker
recognition
Immersive audio. Includes audio acquisition
and reproduction for different environments
Video processing. Includes legacy video and
challenging video transcoding
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Advanced Car Information System (ACIS)
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hArtes ACIS on the road
other sys
(cabin)
media
storage
other systems
connections (radio-TV,
GPS, UMTS, network,
etc.)
Windows
PC
pre
pre
pre
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platform
microphones
ampli
ampli
ampli
loudspeakers
hArtes based ACIS
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remote web
access
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Immersive audio
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hArtes application platform hypothesis
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hArtes HW platform
Scope of the HW platform:
Provide a flexible, reconfigurable platform for the
selected application domain where the hArtes tool chain
can be exercised.
Must provide an heterogeneous, reconfigurable platform
and the appropriate set of interfaces. Detailed
specification ongoing in strict relation with the
Application partners
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HDK dissemination initiative
HDK FREE - hArtes Development Kit with Floating point for Real
time Embedded Equipment
Objective: academic + SME dissemination & hands-on tool for
workshops
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Consortium composition
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Partners:
INDUSTRY: Atmel (it), FAITAL (it), Thales (fr), Thomson
(fr)
SME: LEAFF (it), Scaleo Chip (fr)
ACADEMIA: TU Delft (nl), PoliMi (it), UNIVPM (it), INRIA
(fr), Fraunhofer (de), Imperial College (uk), UNIFE(it),
Université d’Avignon-LIA (fr)
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Partners role
Applications
UNIVPM, FAITAL, Thales, Fraunhofer, Thomson, LIA
Tools / methodologies:
TU Delft, PoliMi, Imperial College, INRIA, LEAFF
Hardware:
Atmel, UNIFE, Scaleo Chip
Integration / Proof of concept
Atmel, UNIVPM, FAITAL, Thales, Fraunhofer,
Thomson
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Partners role
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Project Duration/Budget
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Project Duration: 3 Years
Project Budget: 17 M€
10.5 M€ Funding
– Biggest funding in Embedded Systems
– Highest evaluation score (27)
Work Packages:
WP0.
WP1.
WP2.
WP3.
WP4.
WP5.
Project management.
Requirements for tools and target applications.
Methodology and tool development.
Demonstrations and Evaluations.
System Integration and Validation.
Exploitation and dissemination.
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