Transcript 슬라이드 1
Sungmin Bae, Hyung-Ock Kim, Jungyun Choi, and Jaehong Park Design Technology Infrastructure Design Center System-LSI Business Division Warning This document is intended only for the recipients designated by Samsung Electronics Co. Ltd. (“Samsung”). As it contains the trade secrets and confidential information of Samsung which are protected by Competition Law, Trade Secrets Protection Act and other related laws, this document may not be, in part or in whole, directly or indirectly publicized, distributed, photocopied or used (including in a posting on the Internet where unspecified individuals may access it) by any unauthorized third party. Samsung reserves its right to take legal measures and claim damages against any party that misappropriates Samsung’s trade secrets or confidential information. 1. Motivation 2. Design flow 3. Parallel multiplier 4. Coarse-grained structural placement methodology 5. Experimental results 6. Future works • Data-flow (design structure) awareness is crucial to enhance physical design qualities. • Timing, area, congestion, and power etc. • Structured datapath placement is mostly done manually. • It is generally thought that placement tools do not perform well on the datapath designs. Sum = A + B • Design efforts; days ~ weeks Floorplan Memory macro placement Structured datapath placement Coarser Control granularity Finer 3 • We have added another methodology in the data-flow aware physical design. • Automated extracting and mapping for a synthesized parallel multiplier to guide structural placement of a global placement. Sum = A * B Floorplan Memory Floorplan macro placement Coarser Logic Synthesis Coarser Control granularity Coarse-grained structured Memory macro placement datapath placement Structured datapath placement Control granularity Finer Finer 4 Datapath template Automated datapath extraction and mapping • Identify cells of a synthesized parallel multiplier to be structurally placed • Inherent structural location extractions of the cells RTL code Parsing/Elaboration • Physical bit-slice alignment of the cells • Generate structural relative placement directives • Guide structural placement during global placement 5 library Timing/ Area constraints Logic Synthesis • Analyze data-flow of the multiplier • Structurally mapping the cells on a logical 2-D array Technology Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations Structural templates (Multiplier) Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical aware bit-slice alignment User Dataflow analysis Structural relative placement directives Global Placement Coarse-grained structural placement No Result satisfactory? Yes No • A parallel multiplier is one of the most abundant arithmetic circuits in today’s multi-media feature intensive SoCs. • Parallel multiplier largely consists of three parts. • Partial product generation • Partial product reduction • Carry propagating adder (Final adder) Multiplicand Multiplier Multiplicand Multiplier Partial Product Final Adder Multiplication in dot-notation Final Product Final Product 6 Y2 Y1 Y0 X3 X2 X1 X0 X0Y3 X0Y2 X0Y1 X0Y0 X1Y3 X1Y2 X1Y1 X1Y0 X2Y3 X2Y2 X2Y1 X2Y0 X3Y3 X3Y2 X3Y1 X3Y0 Partial Products Partial Product Reduction Y3 S7 S6 S5 S4 S3 S2 S1 S0 • Partial product generation • Non-booth : it generates the logical product of a multiplicand and multiplier (AND). • Booth (Radix-4) : it reduces the number of partial products to the half. • Partial product reduction • Carry-save adder tree: it reduces every column to 2 output rows using compressor cell. • Carry-propagate adder (final adder) • Carry look ahead adder : it adds the 2 output rows Multiplicand Partial Carry-propagate product adder Partial product generation reduction Multiplier Multiplicand Multiplier Partial Product Partial Products Partial Product Reduction Final Adder Final Product PPi+2j-2 PPi+1j-1PPij PPi-1j+1 A2 B2 Xi 3:2 Yj FA Cout FA C2 Multiplication in dot-notation Final Product C3 S2 P2 G2 PPij A0 B0 A1 B1 Sum FA C1 S1 P1 G1 3:2 S0 P0 G0 Carry-look ahead unit Non-booth C0 Booth Cin • It performs RTL code 1. Identify cells of a synthesized parallel multiplier to be structurally placed • • Parsing/Elaboration 3. 4. The PI cells from the partial product generation The PO cells from the final adder 5. 6. 7. Generate structural relative placement directives Guide structural placement during global placement 8 Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations Tagging structural locations for the PI and PO cells Analyze data-flow of the multiplier Structurally mapping the cells on a logical 2-D array Physical bit-slice alignment of the cells library Timing/ Area constraints Logic Synthesis 2. Inherent structural location extraction of the cells • Technology Structural templates (Multiplier) Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical aware bit-slice alignment User Dataflow analysis Structural relative placement directives Global Placement Coarse-grained structural placement N o Result satisfactory? Yes N o • The PI cells from the partial product generation • The PI cells are retrieved by the immediate fan-out cone cells of the input nets. • A set of nets that to collect the PI cells differs depending on the type of the partial product generation. • Non-booth : multiplicand and multiplier input nets • Booth : multiplicand input nets Multiplicand Multiplier Partial product generation Partial Product Partial Product Reduction Final Adder Final Product Xi Yj Y2 Y1 Y0 X3 X2 X1 X0 X0Y3 X0Y2 X0Y1 X0Y0 X1Y3 X1Y2 X1Y1 X1Y0 X2Y3 X2Y2 X2Y1 X2Y0 X3Y3 X3Y2 X3Y1 X3Y0 PPij Non-booth Y3 S7 Booth 9 S6 S5 S4 S3 S2 S1 S0 • After extracting the PI cells, the PI cells are tagged by 2-D locations of a partial product row and column. • Row inference • Column inference • The row of the PI cell can be inferred by its topologically closest multiplier inputs. • Row inference • i indicates the ith row of the partial product generator. - PIrow(Ck) : the row number of the PI cell Ck PIcol(Ck) : the column number of the PI cell Ck Bmd(Ck) : the closest multiplicand bit of Ck Bmr(Ck) : the closest multiplier bit of Ck PPtype : the partial product type Xi Yj PPij Non-booth Booth • The column of the PI cell can be inferred by its topologically closest and bitslice aligned multiplier output bit. • Topological order propagation is restricted to only follow the same weighted bit-slice along the CSA tree. - Ignoring carry-out pins of the compressor cells. • Column inference • Find topologically closest and bit-slice aligned result. 3:2 3:2 3:2 3:2 Y2 Y1 Y0 X3 X2 X1 X0 X0Y3 X0Y2 X0Y1 X0Y0 X1Y3 X1Y2 X1Y1 X1Y0 X2Y3 X2Y2 X2Y1 X2Y0 X3Y3 X3Y2 X3Y1 X3Y0 3:2 3:2 3:2 S7 Column[i+1] Y3 Column[i] 11 S6 S5 S4 S3 S2 S1 S0 • The PO cells are parts of the final carry propagating adder. • The PO cells are retrieved by the immediate fan-in cone cells of the output nets. • Tags corresponding multiplier output bits to the PO cells Multiplicand Carry-propagate adder Multiplier Partial Product A2 B2 Partial Product Reduction FA FA C2 Final Adder C3 Final Product 12 A1 B1 S2 P2 G2 A0 B0 FA C0 C1 S1 P1 G1 S0 P0 G0 Carry-look ahead unit • It performs 1. 2. RTL code Identify cells of a parallel multiplier to be structurally placed Technology Parsing/Elaboration library Timing/ Area constraints Logic Synthesis Inherent structural location extraction of the cells Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator 3. Structurally mapping the cells on a logical 2-D array Technology independent and dependent optimizations Structural templates (Multiplier) 4. Analyze data-flow of the multiplier Optimized gate-level netlist Structure Extraction and Mapping 5. Structural location inference/ Cell mapping Physical bit-slice alignment of the cells Physical aware bit-slice alignment 6. Generate structural relative placement directives User Dataflow analysis Structural relative placement directives Global Placement 7. Guide structural placement during global placement 13 Coarse-grained structural placement N o Result satisfactory? Yes N o • Data-flow can be analyzed from a global placement • Data-flow can be estimated by relative locations of the input and output related cells. • A method for the data-flow analysis … • Linear regression to get the lines of the input and output related cells. • Analyze the input to output lines’ relation any overlap between the lines? angle of the overlap etc. Top to bottom or left to right etc. ? MSB to LSB or LSB to MSB? 14 • It performs 1. Identify cells of a parallel multiplier to be structurally placed 2. Inherent structural location extraction of the cells 3. Analyze data-flow of the multiplier RTL code Parsing/Elaboration 5. Using the inferred row and column numbers. library Timing/ Area constraints Logic Synthesis Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations 4. Structurally mapping the cells on a logical 2D array • Technology Structural templates (Multiplier) Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical bit-slice alignment of the cells Physical aware bit-slice alignment 6. Generate structural relative placement directives 7. Guide structural placement during global placement User Dataflow analysis Structural relative placement directives Global Placement Coarse-grained structural placement N o Result satisfactory? Yes N o • The PI cells are mapped onto a logical 2-D array according to their tagged row and column numbers. • However, the number of cells inferring to the same location can be uneven due to the local nature of logic synthesis optimizations. • If enough slots are allocated for all the cells, the 2-D array may have uncontrollable aspect ratio which may degrade placement quality. • The maximum number of columns is constrained to control the array dimension. • The number of rows is fixed. • Some mis-mappings are allowed. • Slot sharing between adjacent columns. • There are spacing between the rows of the 2-D array. • Non-guided cells to be placed close to their inherent structural locations. 16 • Min-cost max-flow based cell mapping to maximize the number of mapped PI cells with minimum mis-mapping cost for a given 2-D array. • An initial 2-D slot array may not fully contain all the PI cells. • It allows empty slot sharing between adjacent bit-slice columns. • It iteratively add dummy (empty) column slots at columns with the worst mis-mapping costs during the mapping. PI Cell[i-1,0] PI Cell[i,0] Cost [0,0] Cost [0,1] CostSH [0,0] CostSH [0,0] Cost [0,0] PI Cell[i+1,0] PI Cell[i+1,0] CostDS [0,0] The slots are divided into the three types for each column having different mapping cost weights. Non-shared : mapping weight CostDS [0,0] Cost [0,n] γown j slots m slots Shared : mapping weight γshared k slots Dummy : mapping weight γdummy Column[i-1] Column[i] Column[i+1] Column[i+1] Shared Slot Dummy Shared Slot Slot[i] Capacity = m Capacity = j Capacity = m Capacity = m Capacity = k 17 Mis-mapping cost : γx*|rowcell – rowslot| • HPWL is considered to compensate for net-connection blindness of the mapping as a tiebreaker for the mapping. • Linear programming formulations of the weighted sum of min-cost max-flow for CostMA(ci) and HPWL minimization for CostHPWL(ni) • CostMA(ci) : weighted sum of mis-mapping cost of cell ci • CostHPWL(ni) : weighted sum of mis-mapping cost of cell ci • Gradually add dummy column slots to minimize mis-mapping cost at columns with the worst mis-mapping cost, then solve the linear program iteratively. 18 • It performs 1. Identify cells of a parallel multiplier to be structurally placed 2. Inherent structural location extraction of the cells 3. Analyze data-flow of the multiplier RTL code Parsing/Elaboration 6. Generate structural relative placement directives library Timing/ Area constraints Logic Synthesis Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations 4. Structurally mapping the cells on a logical 2D array 5. Physical bit-slice alignment of the cells Technology Structural templates (Multiplier) Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical aware bit-slice alignment User Dataflow analysis Structural relative placement directives 7. Guide structural placement during global placement Global Placement Coarse-grained structural placement N o Result satisfactory? Yes N o • The logically mapped PI and PO cells are then bit-slice aligned with respect to their physical dimension. • Strict bit-slice alignment : a column width is decided by the widest cell among them - uncontrollable cell alignment size Ci,j-1 i-1,j-1 i-2,j-1 Ci,j Ci-1,j Ci-2,j Ci,j+1 Ci-1,j+1 Ci,j+2 Ci,j+3 Ci-1,j+2 Ci-2,j+1 Ci-1,j+3 Ci-2,j+2 Ci-2,j+3 • Compression alignment : this generates a compact cell cluster - It cannot ensure vertical bit-slice alignment Ci,j-1 Ci-1,j Ci-2,j Ci,j Ci-1,j+1 Ci-2,j+1 Ci,j+1 Ci-1,j+2 Ci-2,j+2 Ci,j+2 Ci,j+3 Ci-1,j+3 Ci-2,j+3 20 • Our method combines the advantages of the aforementioned methods. • Align the columns within a maximum width constraint • It performs bit slice misalignment minimization while ensuring a maximum alignment width. Misalignment at each column Ci,j-1 i-1,j-1 i-2,j-1 Ci,j Ci-1,j Ci-2,j Ci,j+1 Ci,j+2 Ci,j+3 Ci-1,j+1 Ci-1,j+2 Ci-1,j+3 Ci-2,j+1 Ci-2,j+2 Maximum width constraint 21 Ci-2,j+3 • It performs 1. Identify cells of a parallel multiplier to be structurally placed 2. Inherent structural location extraction of the cells 3. Analyze data-flow of the multiplier 4. RTL code Technology Parsing/Elaboration library Logic Synthesis Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations Structurally mapping the cells on a logical 2-D array Structural templates (Multiplier) 5. Physical bit-slice alignment of the cells 6. Generate structural relative placement directives • • The relative row and column locations of the cells The column spaces between the cells Timing/ Area constraints Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical aware bit-slice alignment User Dataflow analysis Structural relative placement directives Global Placement Coarse-grained structural placement 7. Guide structural placement during global placement N o Result satisfactory? Yes N o • After the bit-slice alignment, the structural locations and the cell spacings are transformed into structural relative placement directives. • Relative row and column locations of the cells • Cell spaces between the cells • To accommodate the cell spaces, the number of the array column is set to be twice of the logical 2-D array. • The compression based alignment is used to align the cell. • An estimated dataflow direction is used to set the initial orientations of the arrays for global placement. Cell slots Cell spacing Ci,j-1 Ci,j Ci-1,j Ci-2,j Ci,j+1 Ci,j+2 Ci,j+3 Ci-1,j+1 Ci-1,j+2 Ci-1,j+3 Ci-2,j+1 Ci-2,j+2 Ci-2,j+3 23 Space slots • It performs 1. Identify cells of a parallel multiplier to be structurally placed 2. Inherent structural location extraction of the cells 3. Analyze data-flow of the multiplier RTL code Parsing/Elaboration 6. Generate structural relative placement directives 7. Guide structural placement during global placement library Timing/ Area constraints Logic Synthesis Arithmetic operation extraction Non-arithmetic logic High-level arithmetic optimizations High-level optimizations Datapath generator Technology independent and dependent optimizations 4. Structurally mapping the cells on a logical 2D array 5. Physical bit-slice alignment of the cells Technology Structural templates (Multiplier) Optimized gate-level netlist Structure Extraction and Mapping Structural location inference/ Cell mapping Physical aware bit-slice alignment User Dataflow analysis Structural relative placement directives Global Placement Coarse-grained structural placement N o Result satisfactory? Yes N o • Structural relative placement directives hold the locations of the PI and PO cells. • Non-guided cells are attracted to the PI and PO cells. 13*12 non-Booth multiplier 32*16 Booth multiplier 25 • We implemented the proposed methodology in Tcl and CLP as a linear program solver. • Commercial logic synthesis and P&R tools with industrial designs were used. • About 2%, 42%, and 2% improvements in critical path delay, total negative slack, and total wire-length respectively. • D11 degraded the physical implementation quality, which had about 25% of the inputs are pruned due to constant propagation, and was not sufficient for the approach. Design # Mults Area ratio CPD TNS Wirelength D1 7 0.49 0.94 0.02 0.99 D2 8 0.17 1.00 0.82 0.98 D3 6 0.33 1.00 0.74 0.95 D4 4 0.32 0.97 0.00 0.98 D5 3 0.30 0.99 0.97 1.00 D6 1 0.25 0.98 0.91 0.95 D7 9 0.21 0.98 0.28 0.94 D8 2 0.21 0.99 0.82 0.99 D9 8 0.18 0.99 0.58 1.00 D10 16 0.09 0.96 0.14 0.99 D11 1 0.40 1.03 1.10 1.02 Ave. 6 0.27 0.98 0.58 0.98 26 • A snapshot of D10 27 • To further automate the method, surrounding (placement blockage, macro, and data-flow etc.) awareness is needed. • The multipliers were required to be “naturally” placed in a narrow macro channel, while structural placement method may prevent this kind of placement. 28 • The future works will focus on • Extending the methodology for other synthesized datapath circuits. • Developing regularity measuring methods to avoid structurally mapping insufficiently regular multipliers. • Adding more surround awareness to further automate the methodology. 29