Transcript Clockless Chips

Date: October 26, 2005.
Clockless Chips
Presented by:
K. Subrahmanya Sreshti.
(05IT6004)
School of Information Technology
Indian Institute of Technology, Kharagpur
Presentation flow:
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Introduction.
Problems with synchronous circuits.
Clockless / Asynchronous circuits.
How clockless chips work?
Simplicity in design.
Applications.
Applications (technical perspective).
Challenges.
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Introduction.
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Struggle for the improvement in the microprocessor’s
performance/functioning.
– Pipelining
– (Simultaneous) Multi-threading
}
Synchronous
– Clockless / Asynchronous logic
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Problems with Synchronous Approach
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Distributing the clock globally.
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Wastage of energy.
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Traverse the chip’s longest wires in one clock cycle.
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Order of arrival of the signals is unimportant.
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Clocks themselves consume lot of energy (~30%).
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Synchronous circuit
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Longest path determines
the minimum clock
period.
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Dissipation of energy for
each clock cycle.
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EMI is more in
synchronous elements.
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Clockless chips (Asynchronous logic circuits)
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Colckless chips/Asynchronous/self-timed circuits.
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Functions away from the clock.
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Different parts work at different speeds.
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Hand-off the result immediately.
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Clock time cycle vs. clockless time cycle
Courtesy: Fulcrum Microsystems.
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Courtesy: Computers without clocks – Ivan E Sutherland and Jo Ebergen
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How do they work?
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No pure asynchronous chips are available.
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Uses handshake signals for the data exchange.
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Data moves only when required, not always.
– Minimizes power consumption.
– Less EMI  less noise  more applications.
– Stream data applications.
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Simple and efficient design
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No centralized clock required.
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Standardized components can be used.
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Some features
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Integrated pipelining mode.
– Domino logic.
– Delay – insensitive.
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Two different implementation details
– Dual rail.
– Bundled data.
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Advantages
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Works at its average speed.
 Low power consumption.
 Twice life-time.
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Less heat generated.
 Good to mobile devices.
Less EMI  less noise  more applications.
 Smart cards (due to asynchronous nature).
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Advantages (technical look)
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Asynchronous for higher
performance:
– Data-dependent delays.
– All carry bits need to be
computed.
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Advantages (technical look)…
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Asynchronous for low power:
– Consumes power only when
and where active.
– Rest of the time returns to a
non-dissipating state, until next
activation.
– Illustrated through frequency
divider
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Advantages (technical look)…
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Asynchronous for low power:
– Almost fixed power dissipation is achieved.
– Many applications such as:
• Infrared communication receiver.
• Filter bank for digital hearing.
• In pagers.
• Double battery life.
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Advantages (technical look)…
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Asynchronous for low noise and low emission:
– Digital sub-circuits
• Generates voltage noise (on power lines)
• Induces current on silicon substrate.
• Emits electromagnetic radiation at its clock frequency or its
harmonics.
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Advantages (technical look)…
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Heterogeneous Timing:
– Gate delays.
– Interconnection delays.
– Heterogeneous systems
would increase the delays in
the circuits.
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Challenges
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Interfacing between synchronous and
asynchronous
– Many devices available now are synchronous in nature.
– Special circuits are needed to align them.
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Lack of expertise.
 Lack of tools.
 Engineers are not trained in these fields.
 Academically, no courses available.
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References
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Scanning the Technology: Applications of Asynchronous Circuits
– C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick
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Computers without clocks – Ivan E Sutherland and Jo Ebergen.
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http://ieeexplore.ieee.org/iel5/2/30617/01413111.pdf (October 2001)
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http://csdl2.computer.org/comp/mags/dt/2003/06/d6005.pdf
http://www1.cs.columbia.edu/async/misc/technologyreview_oct_0
1_2001.html
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http://www.technologyreview.com/articles/01/10/tristram1001.asp
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http://www1.cs.columbia.edu/async/misc/economist/Economist_c
om.htm
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Thank you
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