Transcript CS 230 Chapter 3 Arithmetic for Computers

CS 230: Computer Organization
and Assembly Language
Aviral Shrivastava
Department of Computer Science and Engineering
School of Computing and Informatics
Arizona State University
Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary
Jane Irwin, PSU, Ande Carle, UCB
M
C L
Announcements
• Project 4
– MIPS Simulator
– Due Nov 10, 2009
• Alternate Project
• Quiz 5
– Thursday, Nov 19, 2009
– Pipelining
• Finals
–
–
–
–
Tuesday, Dec 08, 2009
Please come on time (You’ll need all the time)
Open book, notes, and internet
No communication with any other human
M
C L
Benefits of Pipelining
• Pipeline latches: pass the status and result of the current instruction to
next stage
• Comparison:
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
Clock
Singlecycle inst.
Ifetch Dec/Reg Exec
Mem
Wr
Ifetch Dec/Reg Exec
sw
lw
Ifetch Dec/Reg Exec
pipelined
Mem
Mem
Ifetch Dec/Reg Exec
Wr
Mem
Ifetch Dec/Reg Exec
Wr
Mem
Wr
M
C L
Passing control w/pipe registers
• Analogy: send instruction with car on assembly line
– “Install Corinthian leather interior on car 6 @ stage 3”
strip off signals for
execution phase
strip off signals for
memory phase
Instruction
WB
IF/ID
Control
Generation
M
WB
EX
M
ID/EX
strip off signals for
write-back phase
WB
RegDst
Branch
MemtoReg
ALUOp
MemRead
RegWrite
ALUSrc
MemWrite
EX/MEM
MEM/WB
M
C L
The hazards of pipelining
• Pipeline hazards prevent next instruction from executing during
designated clock cycle
• There are 3 classes of hazards:
– Structural Hazards:
• Arise from resource conflicts
• HW cannot support all possible combinations of instructions
– Data Hazards:
• Occur when given instruction depends on data from an instruction
ahead of it in pipeline
– Control Hazards:
• Result from branch, other instructions that change flow of program
(i.e. change PC)
M
C L
Instruction 3
Instruction 4
Time
Reg
Reg
DM
Reg
Mem
Reg
DM
Reg
Mem
Reg
DM
Reg
Mem
Reg
ALU
Instruction 2
Mem
DM
ALU
Instruction 1
Reg
ALU
Mem
ALU
Load
ALU
Structural Hazard
DM
What’s the problem here?
4/27/2020
CSE 420: Computer Architecture
Reg
M
C L
6
Structural hazards
• A way to avoid structural hazards is to duplicate
resources
– i.e.: An ALU to perform an arithmetic operation and an adder
to increment PC
• If not all possible combinations of instructions can be
executed, structural hazards occur
• Most common instances of structural hazards:
– When a functional unit not fully pipelined
– When some resource not duplicated enough
7
4/27/2020
CSE 420: Computer Architecture
M
C L
Instruction 2
Stall
Reg
Reg
DM
Reg
Mem
Reg
DM
Reg
Bubble
Bubble
Bubble
Instruction 3
Time
Mem
DM
Bubble
Mem
Reg
Pipeline generally stalled by
inserting a “bubble”
or NOP
4/27/2020
CSE 420: Computer Architecture
ALU
Instruction 1
Reg
ALU
Mem
ALU
Load
ALU
How is it resolved?
Bubble
DM
Reg
M
C L
8
Or alternatively…
Clock Number
Inst. #
LOAD
1
2
3
4
5
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
stall
IF
ID
IF
Inst. i+1
Inst. i+2
Inst. i+3
Inst. i+4
6
Inst. i+5
7
8
9
EX
MEM
WB
ID
EX
MEM
WB
IF
ID
EX
MEM
IF
ID
EX
Inst. i+6
10
• LOAD instruction “steals” an instruction fetch cycle which
will cause the pipeline to stall.
• Thus, no instruction completes on clock cycle 8
4/27/2020
CSE 420: Computer Architecture
M
C L
9
Example: Dual-port vs. Single-port
• Machine A: Dual ported memory (“Harvard Architecture”)
• Machine B: Single ported memory, but its pipelined
implementation has a 1.05 times faster clock rate
• Ideal CPI = 1 for both
• Loads are 40% of instructions executed
SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe)
= Pipeline Depth
SpeedUpB = Pipeline Depth/(1 + 0.4 x 1) x (clockunpipe/(clockunpipe / 1.05)
= (Pipeline Depth/1.4) x 1.05
= 0.75 x Pipeline Depth
SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33
• Machine A is 1.33 times faster
4/27/2020
CSE 420: Computer Architecture
10
M
C L
AND R6, R1, R7
OR R8, R1, R9
XOR R10, R1, R11
Time
Mem
DM
Reg
Reg
DM
Reg
Mem
Reg
DM
Mem
Reg
ALU
SUB R4, R1, R5
Reg
ALU
Mem
ALU
ADD R1, R2, R3
ALU
Illustrating a data hazard
Mem
Reg
ADD instruction causes a hazard in next 3 instructions
b/c register not written until after those 3 read it.
M
C L
One Way to “Fix” a Data Hazard
IM
Reg
DM
Reg
IM
Reg
ALU
O
r
d
e
r
add $1,
ALU
I
n
s
t
r.
Fix data hazard
by waiting –
stall – but
impacts CPI
IM
Reg
stall
stall
sub $4,$1,$5
ALU
and $6,$7,$1
DM
Reg
DM
Reg
M
C L
One Way to “Fix” a Data Hazard
IM
Reg
DM
Reg
IM
Reg
ALU
O
r
d
e
r
add $1,
ALU
I
n
s
t
r.
Fix data hazard
by waiting –
stall – but
impacts CPI
IM
Reg
stall
stall
sub $4,$1,$5
ALU
and $6,$7,$1
DM
Reg
DM
Reg
M
C L
Another Way to “Fix” a Data Hazard
and $6,$7,$1
$8,$1,$1
sw
$4,4($1)
Reg
IM
Reg
IM
Reg
IM
Reg
DM
Reg
DM
Reg
DM
Reg
DM
ALU
or
IM
ALU
sub $4,$1,$5
Reg
ALU
IM
ALU
O
r
d
e
r
add $1,
ALU
I
n
s
t
r.
Fix data
hazards by
forwarding
results as soon
as they are
available to
where they are
needed
Reg
DM
Reg
M
C L
Data Forwarding (aka Bypassing)
• Take the result from the earliest point that it exists in any of
the pipeline state registers and forward it to the functional
units (e.g., the ALU) that need it that cycle
• For ALU functional unit: the inputs can come from any
pipeline register rather than just from ID/EX by
– adding multiplexors to the inputs of the ALU
– connecting the Rd write data in EX/MEM or MEM/WB to either (or
both) of the EX’s stage Rs and Rt ALU mux inputs
– adding the proper control hardware to control the new muxes
• Other functional units may need similar forwarding logic
(e.g., the DM)
• With forwarding can achieve a CPI of 1 even in the presence
of data dependencies
M
C L
OR R8, R1, R9
XOR R10, R1, R11
Time
Mem
DM
Reg
Reg
DM
Reg
Mem
Reg
DM
Mem
Reg
ALU
AND R6, R1, R7
Reg
ALU
SUB R4, R1, R5
Mem
ALU
ADD R1, R2, R3
ALU
When can we forward?
Mem
Reg
SUB gets info.
from EX/MEM
pipe register
AND gets info.
from MEM/WB
pipe register
OR gets info. by
forwarding from
register file
Rule of thumb: If line goes “forward” you can do forwarding.
If its drawn backward, it’s physically impossible.
M
C L
Datapath with Forwarding Hardware
PCSrc
ID/EX
EX/MEM
Control
IF/ID
Add
Shift
left 2
4
PC
Instruction
Memory
Read
Address
Add
Read Addr 1
Data
Memory
Register Read
Read Addr 2Data 1
File
Write Addr
Write Data
16
Sign
Extend
MEM/WB
Branch
ALU
Read
Data 2
Address Read
Data
Write Data
ALU
cntrl
32
ForwardA
EX/MEM.RegisterRd
ForwardB
ID/EX.RegisterRt
ID/EX.RegisterRs
Forward
Unit
MEM/WB.RegisterRd
M
C L
Data Forwarding Control Conditions
1. EX/MEM hazard:
if (EX/MEM.RegWrite
and (EX/MEM.RegisterRd
and (EX/MEM.RegisterRd
ForwardA = 10
if (EX/MEM.RegWrite
and (EX/MEM.RegisterRd
and (EX/MEM.RegisterRd
ForwardB = 10
!= 0)
= ID/EX.RegisterRs))
!= 0)
= ID/EX.RegisterRt))
Forwards the
result from the
previous instr.
to either input
of the ALU
2. MEM/WB hazard:
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd
and (MEM/WB.RegisterRd
ForwardA = 01
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd
and (MEM/WB.RegisterRd
ForwardB = 01
!= 0)
= ID/EX.RegisterRs))
!= 0)
= ID/EX.RegisterRt))
Forwards the
result from the
second
previous instr.
to either input
of the ALU
M
C L
Yet Another Complication!
• Another potential data hazard can occur when there is a
conflict between the result of the WB stage instruction and
the MEM stage instruction – which should be forwarded?
add $1,$1,$3
Reg
IM
Reg
IM
Reg
DM
Reg
DM
ALU
add $5,$1,$4
IM
ALU
O
r
d
e
r
add $1,$6,$2
ALU
I
n
s
t
r.
Reg
DM
Reg
M
C L
Corrected Data Forwarding Control Conditions
2. MEM/WB hazard:
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd != 0)
and (EX/MEM.RegisterRd != ID/EX.RegisterRs)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd != 0)
and (EX/MEM.RegisterRd != ID/EX.RegisterRt)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01
M
C L
Inserting bubbles
Insert Bubble
Hazard
Detection
Unit
ID/EX
Control
0
PC
M
u
x
WB
EX/MEM
M
WB
MEM/WB
EX
M
WB
IF/ID
M
C L
Datapath with Forwarding Hardware
PCSrc
ID/EX
EX/MEM
Control
IF/ID
Add
Shift
left 2
4
PC
Instruction
Memory
Read
Address
Add
Read Addr 1
Data
Memory
Register Read
Read Addr 2Data 1
File
Write Addr
Write Data
16
Sign
Extend
MEM/WB
Branch
ALU
Read
Data 2
Address Read
Data
Write Data
ALU
cntrl
32
EX/MEM.RegisterRd
ID/EX.RegisterRt
ID/EX.RegisterRs
Forward
Unit
MEM/WB.RegisterRd
M
C L
Yoda says…
Death is a natural part of life. Rejoice for those
around you who transform into the Force.
Mourn them do not. Miss them do not
M
C L