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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
The Inverter
© Digital Integrated Circuits2nd
Inverter
DIGITAL GATES
Fundamental Parameters
Functionality
Reliability, Robustness
Area
Performance
DC Characteristics
Speed (delay)
Power Consumption
© Digital Integrated Circuits2nd
Inverter
Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
(a) Inductive coupling
(b) Capacitive coupling
(c) Power and ground
noise
© Digital Integrated Circuits2nd
Inverter
The Ideal Gate
Vout
Ri =
Ro = 0
g=
Vin
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Rn
V in = V DD
© Digital Integrated Circuits2nd
V in = 0
Inverter
Mapping between analog and digital signals
"1"
V
OH
V
IH
V(y)
V
OH
Slope = -1
Undefined
Region
"0"
V
IL
V
OL
© Digital Integrated Circuits2nd
Slope = -1
VOL
V
V
IL IH
V(x)
Inverter
Definition of Noise Margins
"1"
V
OH
NMH
Noise Margin High
Noise Margin Low
NML
V
IH
Undefined
Region
V
IL
V
OL
"0"
Gate Output
© Digital Integrated Circuits2nd
Gate Input
Inverter
The Regenerative Property
...
v1
v0
v2
v3
v5
v4
v6
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
finv(v)
v0, v2, ...
(b) Regenerative gate
© Digital Integrated Circuits2nd
f(v)
v0, v2, ...
(c) Non-regenerative gate
Inverter
Fan-in and Fan-out
(a) Fan-out N
M
N
© Digital Integrated Circuits2nd
(b) Fan-in M
Inverter
The CMOS Inverter: A First
Glance
V DD
V in
V out
CL
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
© Digital Integrated Circuits2nd
Inverter
VTC of Real Inverter
5.0
Vout (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
1.0
© Digital Integrated Circuits2nd
2.0
3.0
Vin (V)
4.0
5.0
Inverter
CMOS Inverter: Transient Response
V DD
V DD
tpHL = f(R on .C L )
= 0.69 R on C L
Rp
V out
V out
CL
CL
Rn
V in = 0
V in = V DD
(a) Low-to-high
(b) High-to-low
© Digital Integrated Circuits2nd
Inverter
Delay Definitions
Vin
50%
t
Vout
t
pHL
t
pLH
90%
50%
10%
tf
© Digital Integrated Circuits2nd
t
tr
Inverter
Ring Oscillator
v1
v0
v0
v2
v1
v3
v4
v5
v5
T = 2 tp N
© Digital Integrated Circuits2nd
Inverter
Power Dissipation
© Digital Integrated Circuits2nd
Inverter
Voltage
Transfer
Characteristic
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
© Digital Integrated Circuits2nd
Inverter
DC Operation:
Voltage Transfer Characteristic
V(y)
V
dVo/dVi =-1
OH
f
V(x)
V(y)
V(y)=V(x)
NML
V
LT
Switching Logic Threshold
NMH
V OL
V OL
VIL VIH
V
OH
V(x)
Nominal Voltage Levels
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter Load Characteristics
I n,p
V in = 0
V in = 5
NMOS
PMOS
V in = 4
V in = 1
V in = 4
V in = 3
V in = 2
V in = 3
V in = 4
V in = 3
V in = 2
Vin = 1
V in = 2
V in = 0
V in = 5
Vout
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter VTC
NMOS off
PMOS lin
NMOS sat
PMOS lin
4
PMOS: linear if Vsg –Vtp > Vsd
•Vo > Vin +Vtp
Vou t
5
Vin < Vtn -NMOS Off
Vin > Vdd – Vtp -PMOS Off
3
2
VOH: PMOS(lin) & NMOS(off)
VOL: PMOS(off) & NMOS(lin)
VIH: PMOS(sat) & NMOS(lin)
VIL: PMOS(lin) & NMOS(sat)
VLT: PMOS(sat) & NMOS(sat)
NMOS sat
PMOS sat
NMOS lin
PMOS sat
1
NMOS: Linear if Vgs-Vtn > Vds
•Vo < Vin –Vtn
1
© Digital Integrated Circuits2nd
2
3
4
NMOS lin
PMOS off
5
Vin
Inverter
CMOS Inverter VTC
VOH: PMOS(lin) & NMOS(off) = Vdd
VOL: PMOS(off) & NMOS(lin) = Gnd
VIH: PMOS(sat) & NMOS(lin): Solve:
p
2
(Vdd VIH | Vtp |)2
n
2
p pCox
Wp
Lp
& n nCox
Wn
Ln
[2(VIH Vtn )Vo Vo ]
2
p
p
dV0
1 VIH (1 ) 2V0 Vtn
(Vdd | Vtp |)
dVin
n
n
VIL: PMOS(lin) & NMOS(sat): Solve:
n
(VIL Vtn )
2
p
[2(Vdd VIL | Vtp |)(Vdd Vo ) (Vdd Vo ) 2 ]
2
2
dV0
1 VIL (1 n ) 2V0 n Vtn Vdd | Vtp |
dVin
p
p
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter VTC
VLT: PMOS(sat) & NMOS(sat):
p
2
(Vdd VLT | Vtp |) 2
VLT
Vtn
n
2
(VLT Vtn ) 2
p
n (Vdd | Vtp |)
p
1
n
If Vtn = Vtp & p = n VLT = Vdd/2: Gives a symmetric Inverter!
© Digital Integrated Circuits2nd
Inverter
Simulated VTC
Vout (V)
4.0
2.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
Vin (V)
© Digital Integrated Circuits2nd
Inverter
Gate Logic Switching Threshold
4.0
V LT
3.0
2.0
Vtn
p
1.00.1
n (Vdd | Vtp |)
VLT
p
1
n
© Digital Integrated Circuits2nd
0.3
1.0
p /n
3.2
10.0
Inverter
Inverter Gain
0
-2
-4
gain
-6
-8
-10
-12
-14
-16
-18
0
0.5
1.5
1
2
2.5
V (V)
© Digital Integrated
in
Circuits2nd
Inverter
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
V (V)
in
© Digital Integrated Circuits2nd
2
2.5
0
0
0.05
0.1
V (V)
0.15
0.2
in
Inverter
Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
© Digital Integrated Circuits2nd
Inverter
Propagation Delay
© Digital Integrated Circuits2nd
Inverter
Delay Definitions
Vin
50%
t
Vout
t
pHL
t
pLH
90%
50%
10%
tf
© Digital Integrated Circuits2nd
t
tr
Inverter
CMOS Inverter: Transient Response
VDD
tpHL = f(R on.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
© Digital Integrated Circuits2nd
t
Inverter
CMOS Inverter Propagation Delay
V DD
tpHL = C
L
V swing /2
Iav
V out
Iav
CL
I (Vo Vdd / 2) I (Vo 0)
I av
2
t pHL
CL (Vdd / 2)
( n / 2)(Vdd Vtn ) 2
~
V in = V
DD
© Digital Integrated Circuits2nd
CL
k n V DD
Inverter
CMOS Inverter Propagation Delay
V DD
Vo
VH
NMOS(sat)
Vdd
Vdd-Vtn
NMOS(lin)
V out
VL
CL
to t1
t2
Time
VL Vdd / 2
t pHL CL
V in = V
DD
© Digital Integrated Circuits2nd
VH
dVo
I n (V0 )
Inverter
CMOS Inverter Propagation Delay
VL Vdd / 2
t pHL CL
VH
dVo
CL
I n (V0 )
VOH Vtn
VOH
n
2
t pHL
CL
n (VOH
dVo
(VOH Vtn )
CL
2
Vdd / 2
VOH Vtn
n
2
dVo
[2(VOH Vtn )Vo Vo ]
2
4(VOH Vtn )
2Vtn
ln
1
Vtn )
(VOH VOL )
(VOH Vtn )
Similarly:
t pLH
4(VOH | Vtp |)
CL
2 | Vtp |
ln
1
p (VOH | Vtp |) (VOH | Vtp |)
(
V
V
)
OL
OH
© Digital Integrated Circuits2nd
Inverter
CMOS Inverter Rise & Fall Time
Similarly, Fall Time:
t HL
2(VH Vtn )
CL
2Vtn
ln
1
n (VH Vtn ) (VH Vtn )
VL
Similarly, Rise Time:
t LH
2(VH | Vtp |)
CL
2 | Vtp |
ln
1
p (VH | Vtp |) (VH | Vtp |)
VL
© Digital Integrated Circuits2nd
Inverter
Computing the Capacitances
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
© Digital Integrated Circuits2nd
Vin
Vout
CL
Inverter
The Miller Effect
Cgd1
V
Vout
Vout
V
Vin
M1
V
2Cgd1
M1
V
Vin
“A capacitor experiencing identical but opposite voltage swings
at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”
© Digital Integrated Circuits2nd
Inverter
Computing the Capacitances
© Digital Integrated Circuits2nd
Inverter
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
0
© Digital Integrated Circuits2nd
0.2
0.6
0.4
trise (nsec)
0.8
1
Inverter
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
© Digital Integrated Circuits2nd
Inverter
NMOS/PMOS ratio
-11
5
x 10
4.5
tpHL
tpLH
= Wp/Wn
tp(sec)
tp
4
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
© Digital Integrated Circuits2nd
Inverter
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
Self-loading effect:
Intrinsic capacitances
dominate
2.8
2.6
2.4
2.2
2
2
4
6
© Digital Integrated Circuits2nd
8
S
10
12
14
Inverter
Design for Performance
Keep capacitances
small
Increase transistor sizes
watch out for self-loading!
Increase
VDD (????)
© Digital Integrated Circuits2nd
Inverter
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
0
© Digital Integrated Circuits2nd
0.2
0.4
0.6
trise (nsec)
0.8
1
Inverter
Inverter Sizing
© Digital Integrated Circuits2nd
Inverter
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
© Digital Integrated Circuits2nd
Inverter
Inverter Delay
• Minimum length devices, L=0.7m
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
WP
RP Runit
Wunit
Delay (D):
1
WN
Runit
Wunit
tpHL = (ln 2) RNCL
Load for the next stage:
© Digital Integrated Circuits2nd
2W
W
1
RN RW
tpLH = (ln 2) RPCL
C gin
W
3
Cunit
Wunit
Inverter
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
© Digital Integrated Circuits2nd
Inverter
Inverter with Load
CP = 2Cunit
Delay
2W
W
Cint
CL
CN = Cunit
Load
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
© Digital Integrated Circuits2nd
Inverter
Delay Formula
Delay ~ RW Cint C L
t p kRW Cint 1 C L / Cint t p 0 1 f /
Cint = Cgin with 1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
© Digital Integrated Circuits2nd
Inverter
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
C gin, j 1
t pj ~ Runit Cunit 1
C
gin
,
j
N
N
C gin, j 1
, C gin, N 1 C L
t p t p , j t p 0 1
C
j 1
i 1
gin, j
© Digital Integrated Circuits2nd
Inverter
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j C gin, j 1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
© Digital Integrated Circuits2nd
Inverter
Optimum Delay and Number of Stages
When each stage is sized by f and has same eff. fanout f:
f N F CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay
t p Nt p 0 1 N F /
© Digital Integrated Circuits2nd
Inverter
Example
In
C1
Out
1
f
f2
C L= 8 C 1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
© Digital Integrated Circuits2nd
Inverter
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
CL F Cin f N Cin with N
ln F
ln f
t p 0 ln F f
t p Nt p 0 F / 1
ln f ln f
t p t p 0 ln F ln f 1 f
0
2
f
ln f
1/ N
For = 0, f = e, N = lnF
© Digital Integrated Circuits2nd
f exp1 f
Inverter
Optimum Effective Fanout f
Optimum f for given process defined by
f exp1 f
fopt = 3.6
for =1
© Digital Integrated Circuits2nd
Inverter
Impact of Self-Loading on tp
No Self-Loading, =0
With Self-Loading =1
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
u
© Digital Integrated Circuits2nd
Inverter
Normalized delay function of F
t p Nt p 0 1 N F /
© Digital Integrated Circuits2nd
Inverter
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
© Digital Integrated Circuits2nd
22.6
Inverter
Power
Dissipation
© Digital Integrated Circuits2nd
Inverter
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
© Digital Integrated Circuits2nd
Inverter
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = C
L
* V dd2
Power = Energy/transition * f = C L * V dd2 * f
Not a function of transistor sizes!
Need to reduce C L , V dd, and f to reduce power.
© Digital Integrated Circuits2nd
Inverter
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0 1 = CL Vdd Vdd – Vt
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
© Digital Integrated Circuits2nd
Inverter
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
EN = CL V dd2 n N
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N
P
= lim -------- f
= lim -----------C V
f clk
avg N N
clk
dd
N N
L
0 1 =
n N
lim -----------N N
P avg = 0 1 C Vdd 2 f clk
L
© Digital Integrated Circuits2nd
Inverter
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
© Digital Integrated Circuits2nd
1.0
2.0
3.0
Vin (V)
4.0
5.0
Inverter
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,
but can’t do this for cascade logic, so ...
© Digital Integrated Circuits2nd
Inverter
Minimizing Short-Circuit Power
8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
Vdd =1.5
0
0
1
2
3
4
5
t /t
sin sout
© Digital Integrated Circuits2nd
Inverter
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
Sub-Threshold
Current Dominant Factor
in low-energy
circuit design!
© Digital Integrated Circuits2nd
Inverter
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS A
2
JS = JS
1-5pA/
for aat1.2
m CCMOS
technology
= 10-100
pA/m2
25deg
for 0.25m
CMOS
m
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
© Digital Integrated Circuits2nd
Inverter
Subthreshold Leakage Component
© Digital Integrated Circuits2nd
Inverter
Static Power Consumption
Vd d
Istat
Vo ut
Vin =5V
CL
Pstat = P(In=1).Vdd . Istat
Wasted•energy
… over dynamic consumption
Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could
help reducing energy in others (e.g. sense amps)
© Digital Integrated Circuits2nd
Inverter
Principles for Power Reduction
Prime
choice: Reduce voltage!
Recent years have seen an acceleration in
supply voltage reduction
Design at very low voltages still open question
(0.6 … 0.9 V by 2010!)
Reduce
switching activity
Reduce physical capacitance
Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47
© Digital Integrated Circuits2nd
Inverter
Impact of
Technology
Scaling
© Digital Integrated Circuits2nd
Inverter
Goals of Technology Scaling
Make
things cheaper:
Want to sell more functions (transistors) per
chip for the same money
Build same products cheaper, sell the same
part for less money
Price of a transistor has to be reduced
But
also want to be faster, smaller, lower
power
© Digital Integrated Circuits2nd
Inverter
Technology Scaling
Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per generation
Technology generation spans 2-3 years
© Digital Integrated Circuits2nd
Inverter
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of Introduction
1999
Technology node
[nm]
180
Supply [V]
1.5-1.8
Wiring levels
2000
2001
2004
2008
2011
2014
130
90
60
40
30
1.5-1.8
1.2-1.5
0.9-1.2
0.6-0.9
0.5-0.6
0.3-0.6
6-7
6-7
7
8
9
9-10
10
Max frequency
[GHz],Local-Global
1.2
1.6-1.4
2.1-1.6
3.5-2
7.1-2.5
11-3
14.9
-3.6
Max P power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
© Digital Integrated Circuits2nd
Inverter
ITRS Technology Roadmap
Acceleration Continues
© Digital Integrated Circuits2nd
Inverter
Technology Scaling (1)
Minimum Feature Size (micron)
10
10
10
10
2
1
0
-1
-2
10
1960
1970
1980
1990
2000
2010
Year
Minimum Feature Size
© Digital Integrated Circuits2nd
Inverter
Technology Scaling (2)
Number of components per chip
© Digital Integrated Circuits2nd
Inverter
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
© Digital Integrated Circuits2nd
Inverter
Technology Scaling (4)
/
x4
3
1
0.1
0.01
80
MPU
DSP
85
90
Year
(a) Power dissipation vs. year.
95
1000
3
10
ars
e
y
0.7
100
Power Dissipation (W)
100
Power Density (mW/mm2 )
ears
x1.4 / 3 y
10
1
1
Scaling Factor
(normalized by 4m design rule)
(b) Power density vs. scaling factor.
From Kuroda
© Digital Integrated Circuits2nd
Inverter
10
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling
most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
© Digital Integrated Circuits2nd
Inverter
Scaling Relationships for Long Channel Devices
© Digital Integrated Circuits2nd
Inverter
Transistor Scaling
(velocity-saturated devices)
© Digital Integrated Circuits2nd
Inverter
Processor Scaling
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
© Digital Integrated Circuits2nd
Inverter
Processor Power
P. Gelsinger: Processors for the New Millenium, ISSCC 2001
© Digital Integrated Circuits2nd
Inverter
Processor Performance
P. Gelsinger: Processors for the New Millenium, ISSCC 2001
© Digital Integrated Circuits2nd
Inverter
2010 Outlook
Performance 2X/16 months
1 TIP (terra instructions/s)
30 GHz clock
Size
No of transistors: 2 Billion
Die: 40*40 mm
Power
10kW!!
Leakage: 1/3 active Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
© Digital Integrated Circuits2nd
Inverter
Some interesting questions
What
will cause this model to break?
When will it break?
Will the model gradually slow down?
Power and power density
Leakage
Process Variation
© Digital Integrated Circuits2nd
Inverter