Transcript ENGR 2720 Chapter 7 - UNT College of Engineering

ENGR 2720 Chapter 7
Digital Arithmetic
And
Arithmetic Circuits
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Chapter 7 Homework
7.1 (a & f), 7.2 (a & h), 7.3 (a & h),
7.5, 7.11 a & e, 7.12 a & g, 7.13a,
7.17, 7.21, 7.36, 7.37
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Signed/Unsigned Binary
Numbers
• Signed Binary Number:
– A binary number of fixed length whose sign (+/–) is
represented by one bit (usually MSB) and its
magnitude by the remaining bits.
• Unsigned Binary Number:
– A binary number of fixed length whose sign is not
specified by a bit. All bits are magnitude and the
sign is assumed +.
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Unsigned Binary Arithmetic
• Sum:
– Result of an Addition Operation of two (or more)
binary numbers (operands).
• Carry:
– A digit (or bit) that is carried over to the next most
significant bit during an n-Bit addition operation.
• The carry bit is a 1 if the result was too large to
be expressed in n bits.
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Basic Rules (Unsigned)
1  carry to next  1111
10010
10101110
 1010
11100
 10010011
101000001
Carry out bit
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Basic Subtraction
• Basic Subtraction of x = a – b, with a =
minuend, b = subtrahend, and x =
difference or result.
• Requires a Borrow Bit if a < b.
• There are other forms of subtraction such
as 2’s Complement Addition used by
microprocessors (such as in a PC).
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Binary Subtraction with Borrow
Examples
1110
110(10)
- 1001
100 1
10000
010 1
0111(10) Borrow ripples to LSB
- 101
Borrow Stage
10 1
0101 1
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Signed Binary Numbers
• Sign Bit:
– A bit (usually the MSB) that indicates whether
a number is positive (= 0) or negative (= 1).
• Magnitude Bits:
– The bits of a signed binary number that tell
how large it is in value.
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Signed Binary Numbers
• True-Magnitude Form:
– A form of signed binary whose magnitude bits are the
TRUE binary form (not complements).
• 1’s Complement:
– A form of signed binary in which negative numbers
are created by complementing all bits.
• 2’s Complement:
– A form of signed binary in which the negative
numbers are created by complementing all the bits
and adding a 1 (1’s Complement + 1).
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True-Magnitude Form
•
•
•
•
•
5-Bit Numbers Negative Sign (S = 1)
+25 = 011001 (Note sign bit (MSB) Sign = 0)
–25 = 111001 (Same as +25 with sign = 1)
+12 = 001100
–12 = 101100
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1’s Complement Form
•
•
•
•
•
8-Bit 1’s Complement Negative (S = 1)
+57 = 00111001
–57 = 11000110 (All Bits Inverted)
+72 = 01001000
–72 = 10110111
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2’s Complement Form
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Signed Binary Addition (8-Bit)
Signed Addition Positive (S = 0)
+30 = 00011110
+75 = 01001011
105
01101001
Similar to binary addition with a sign bit.
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Subtraction with 1’s
Complement
• Add the 1’s Complement and then Carry.
(80 – 65)
 80  0101 0000 ( 80)  0101 0000
- 65  0100 0001 ( 65)  10111110 (1' s Comp 65)
1 0000 1110
1
0000 1111
• Uses an End around carry addition method.
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2’s Complement Subtraction
• Add 2’s Complement to Minuend.
(80 – 65)
Discord Carry Bit From Results
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Negative Results
• If the True-Magnitude Form is used for
subtraction, the results are incorrect.
• If the result is from 1’s or 2’s Complement
and the result is negative (S = 1), the
magnitude is found by taking the
complement of the result.
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Negative Result Example
Thus, = -1510
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Range of Signed Numbers
• Range of Positive Numbers is 0 to 2n – 1 for a
number with n magnitude bits.
• Range of Negative Numbers is –1 to –2n for a
number with n magnitude bits.
• 8-Bit Example:
8-Bit Number Range is –2n  x  +2n – 1
or –128 to +127
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Sign Bit Overflow
• Overflow:
– An erroneous carry into the sign bit of a
signed binary number
– Results from a sum or difference that is
larger than can be represented by the
magnitude bits.
• Results in a False Positive or False
Negative Number.
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False Negative Overflow
• Addition of two 8-Bit Positive Numbers:
 75 
0100 1011
 96   0110 0000
1010 1011
Result is Negative (False)
• Two positive numbers added with a result
greater than the range of +127 for 8-bit numbers
causes an overflow.
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False Positive Overflow
• Addition of two 8-Bit Negative Numbers:
 80 
10110000
 65   10111111
0110 1111
Result is Positive (False)
• Two Negative numbers were added to produce a
False Positive Result due to overflowing the negative
range of 8-bit numbers (0 to –127).
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Hexadecimal Addition
• Similar to decimal addition with a range of
digits of 0 to 9 and A to F.
• Examples:
F+1
= 10
F+F
= 1E
F + F + 1 = 1F
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Hexadecimal Addition
Hex
26B3H
 1A9CH
Decimal Equivalent
( 2)( 6) (11)( 3)
( 1)(10)( 9)(12)
(3) (16)(20)(15)
• For sums greater than 15, subtract 16 and carry 1 to the
next position.
Carry  1
1
( 2)( 6) (11)(3)
( 1)(10)( 9)(12)
( 4)( 1) ( 4)(15)
Hex 
414FH
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Hexadecimal Subtraction
Hex
Decimal Equivalent
26B3H
(2)(6)(11)(3)
 1A9CH
(1)(10)(9)(12)
To subtract the least significant digit, borrow 10H (1610 )
from the previous position.
Borrow  1  1
(1)(16  6) (10)(16  3)
Hex 
- (1) (10)
(9) (12)
(0)(12)
(1) ( 7)
C17H
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Hexadecimal Subtraction
2F00H – 4000H
Convert 4000H to hexadecimal equivalent of 2’s
complement:
FFFF
4000
BFFF
+1
C000
Add numbers:
2F00
+ C000
EF00H
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Hexadecimal Subtraction
a.
b.
c.
d.
e.
2F00H – 4000H
Converting 4000 to binary = 0100 0000 0000 0000
Take 1’s complement =
1011 1111 1111 1111
Take 2’s complement =
+1 +1 +1 +1
1100 0000 0000 0000
Change to Hexadecimal =
C000H
Add numbers:
2F00
+ C000
EF00H
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BCD Codes
• BCD Code (Binary-Coded Decimal): A code
used to represent each decimal digit of a
number by a 4-Bit Binary Value.
• Valid Digits for 0 to 9 are 0000 to 1001.
– The binary codes 1010 to 1111 are invalid
• Called an 8421 Code due to the decimal weight
of each bit position.
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BCD Examples
• Each digit is a 4-Bit Binary group:
(84)10 = 1000 0100
(4987)10 = 0100 1001 1000 0111BCD
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BCD Examples
1
The output range of a 4.5-digit BCD adder is 0000 to 19999.
The carry bit is considered a half-digit since it can be only 0 or 1.
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Excess-3 Code
• A BCD Code formed by adding 3 (0011) to its
true 4-bit binary value.
• Excess-3 is a self-complementing code:
– A negative code equivalent can be found by inverting
the binary bits of the positive code
• Inverting the bits of the Excess-3 digit yields 9’s
Complement of the decimal equivalent.
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Excess-3 Examples
• 3 = 0011 + 0011 = 0110 = 6 in E3.
• 1 = 0001 + 0011 = 0100 = 4 in E3.
• If we complement 1 = 1011 in E3, this is the
code for an 8 (1011 – 011 = 1000)
which is the 9’s Complement of 1 = (9 – 1) = 8.
• Useful for performing decimal arithmetic digitally
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Gray Code
• A binary code that progresses so that only one
bit changes between two successive codes.
000
001
010
011
010
110
111
101
100
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ASCII Code
• American Standard Code for Information
Interchange.
• A seven-bit alphanumeric code used to
represent text letters, numerals,
punctuation, and special controls.
• An expanded 8-bit form is becoming more
widespread.
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Binary Adders
• Half Adder (HA): A circuit that will add two
bits and produce a sum bit and a carry bit.
• Full Adder (FA): A circuit that will add a
carry bit from another HA or FA and two
operand bits to produce a sum bit and a
carry bit.
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Basic HA Addition
• Binary Two-Bit Addition Rules:
0 + 0 = 00
0 + 1 = 01
1 + 1 = 10
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HA Circuit
• Basic Equations: S = A XOR B, C = A and B
where S = Sum and C = Carry.
• Truth Table for HA Block:
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Full Adder Basics
• Adds a CIN input to the HA block.
• Equations are modified as follows:
COUT  ( A  B ) CIN  A B

 ( A  B )  CIN
• A FA can be made from two HA blocks and
an OR Gate.
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Full Adder Basics
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Full Adder Basics
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Full Adder Basics
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Parallel Adders
• A circuit, consisting of n full adders, that
will add n-bit binary numbers.
• The output consists of n sum bits and a
carry bit.
• COUT of one full adder is connected to CIN
of the next full adder.
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4-Bit Parallel Adder
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4-Bit Parallel Adder
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Ripple Carry – 1
• In the n-Bit Parallel Adder (FA Stages) the
Carryout is generated by the last stage
(FAN).
• This is called a Ripple Carry Adder
because the final carryout (Last Stage) is
based on a ripple through each stage by
CIN at the LSB Stage.
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Ripple Carry – 2
• Each Stage will have a propagation delay
on the CIN to COUT of one AND Gate and
one OR Gate.
• A 4-Bit Ripple Carry Adder will then have a
propagation delay on the final COUT of 4 
2 = 8 Gates.
• A 32-Bit adder such as in an MPU in a PC
could have a delay of 64 Gates.
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Ripple Carry - 3
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Look-Ahead Carry – 1
• Fast Carry or Look-Ahead Carry:
– A combinational network that generates the
final COUT directly from the operand bits (A1 to
An, B1 to Bn).
– It is independent of the operations of each FA
Stage (as the ripple carry is).
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Look Ahead Carry – 2
• Fast Carry has a small propagation delay
compared to the ripple carry.
• The fast carry delay is 3 Gates for a 4-Bit
Adder compared to 8 for the Ripple Carry.
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4-Bit Fast Carry Circuit
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Subtractor (2’s Complement)
• The concept of Subtraction using 2’s
Complement addition allows a Parallel FA
to be used.
• The subtract operation involves adding the
inverse of the subtrahend to the minuend
and then adding a 1.
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Subtractor (2’s Complement)
• Difference A  B  A  B  1
• This operation can be done in a parallel n-Bit FA
by inverting (B1 to Bn) and connecting CIN at the
LSB Stage to +5 V.
• The circuit can be modified to allow either the
ADD or SUBTRACT operation to be performed.
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Subtractor (2’s Complement)
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Parallel Binary Adder/Subtractor
• XOR gates are used as programmable
inverters to pass binary numbers (e.g.,
B1B2B3B4) to the parallel adder in true or
complemented form.
• When ADD/SUB  1, B is complement ed.
When ADD/SUB  0, B is in its true form.
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Parallel Binary Adder/Subtractor
1
X
Y
B’
B
B
B
B
0
X=1
X=0
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Overflow
• If the sign bits of both operands are the
same and the sign bit of the sum is
different from the operand sign bits, an
overflow has occurred.
• Overflow is not possible if the sign bits of
the operands are different from each other.
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Overflow Examples
• Adding two 8-bit negative numbers:
80H 1000 0000
 80H  1000 0000
100H 10000 0000 (Sign bit overflow V
;  1)
• Adding two 8-bit positive numbers:
7FH 01111111
 01H 0000 0001
80H 1000 0000 (Sign bit overflow V
;  1)
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Overflow 8-bit Parallel Adder
S A A 7 A 6 A5 A4 A3 A2 A1
(SA  Sign bit of A)
SB B7 B6 B5 B4 B3 B2 B1
(SB  Sign bit of B )
S  S7 S6 S5 S4 S3 S2 S1
(S  Sign bit of sum)
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Overflow Detector Truth Table
SA
SB
S
V
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
0
V  SASBS  SASBS
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Overflow Detector Truth Table
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BCD Adder
• A Parallel Adder whose output sum is in
groups of 4 bits, each representing a BCD
(8421) Digit.
• Basic design is a 4-Bit Binary Parallel
Adder to generate a 4-Bit Sum of A + B.
• Sum is input to the four-bit input of a
Binary-to-BCD Code Converter.
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BCD Adder
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