Transcript LAB Topics

Workshop Topics - Outline
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Workshop 1 - Introduction
Workshop 2 - module instantiation
Workshop 3 - Lexical conventions
Workshop 4 - Value Logic System
Workshop 5 - Data types A
Workshop 6 - Data types B
Workshop 7 - Operators
Workshop 8 - Signed arithmetic
Workshop 9 - Behavioral modeling A
Workshop 10 - Behavioral modeling B
Workshop 11 - Behavioral modeling C
Workshop 12 - Data flow modeling
Workshop 13 - Coding Styles
1
Verilog Value Set
4 value logic system:
0
represents low logic level or false condition
1
represents high logic level or true condition
X
represents unknown logic level
Z
represents high impedance logic level
Note: x and z have limited use for synthesis
2
Four-valued Logic System
 Logical operators work on three-valued logic (0, 1, X)
in1
in2
in1
in2
0
1
X
Z
3
0
0
0
0
0
1
0
1
X
X
out
X
0
X
X
X
Z
0
X
X
X
Output 0 if one input is 0
Output X if both
inputs are gibberish
The Power of Verilog: Integer Arithmetic
 Verilog’s built-in arithmetic makes a 32-bit adder easy:
module add32 (a, b, sum) ;
input [31:0] a, b ;
output wire [31:0] sum ;
assign sum = a + b ;
endmodule
 A 32-bit adder with carry-in and carry-out:
module add32_carry (a, b, cin, sum, cout) ;
input [31:0] a, b ;
input cin ;
output wire [31:0] sum ;
output wire cout ;
assign {cout, sum} = a + b + cin ; // Concatenation
endmodule
4
Quiz – Practice
 Practice writing the following numbers:
1. Decimal number 123 as a sized 8-bit number
in binary.
Use _ for readability.
8’b0111_1011
2. A 16-bit hexadecimal unknown number
with all x’s.
16’hX
3. A 4-bit negative 2 in decimal.
Write the 2’s complement for this number.
-4’d2
4’d14
4. An unsized hex number 1234.
’h1234
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Quiz – Practice cont.
 Are the following legal strings?
If not, write the correct strings.
a. “this is a string ‘displaying
the % sign”
Not-legal, string must be contained on a single line
b. “out = in1 + in2”
Legal
c. “Please ring the bell \007”
Legal
d. “This is a backslash \ character\n”
Not-legal, includes \n = new line
6
Quiz – Practice cont.
 Are these legal identifiers?
a. system1
Legal
b. 1reg
Not-legal, starts with a digit (number)
c. $latch
Not-legal, starts with a $ sign
d. exec$
Legal
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Quiz – Practice cont.
 Declare the following variables in Verilog:
a. An 8-bit vector net called a_in
wire [7:0] a_in ;
b. A 32-bit storage register called address.
Bit 31 must be the MSB (Little- Endian).
reg [31:0] address ;
c. Set the value of the register to a 32-bit decimal
number equal to 3
address = 32’d3 ;
d. An integer called count // integer = 32bits register
integer count ;
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Quiz – Practice cont.
e. A time variable called snap_shot // time = 64bits register
time snap_shot ;
f. An-array called delays. Array contains 20 elements
of the type integer
integer delays[0:19] ;
g. A memory MEM containing 256 words of 64 bits each
reg [63:0] MEM[0:255] ;
h. A parameter cache_size equal to 512
// a constant value declared within a module
parameter cache_size = 512 ;
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CPU Address Bus Buffer Example
module addr_buff(addr, abus, wr) ;
input [31:0] addr ;
3’S
input wr ;
output [31:0] abus ;
addr
assign abus = (wr)? addr : 32’bZ ;
endmodule
module addr_buff_tb ; // test bench
reg [31:0] addr ;
3’S
reg wr ;
wr
wire [31:0] abus ;
addr_buff UUT(addr, a_bus, wr) ; // UUT instantiation
initial
begin
addr = 32’hAAAAAAAA ; wr = 0 ;
#1 wr = 1 ;
#1 addr = 32’h55555555 ;
#1 wr = 0 ;
#1 $finish ;
end
endmodule
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abus
CPU Address Bus Buffer Simulation
 Simulation results
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CPU Data Bus Buffer Example
module data_buff(dout, control, dbus) ;
input [31:0] dout ; // write data
dout
dbus
3’S
input wr ;
inout [31:0] dbus ;
wr
assign dbus = (control)? dout : 32’bZ ;
endmodule
Read data
module data_buff_tb ; // test bench
reg [31:0] dout, Dbus ; // Dbus – data from external memory
reg control ;
wire [31:0] dbus ;
data_buff UUT(dout, wr, dbus) ; // UUT instantiation
initial
begin
dout = 32’hAAAAAAAA ; control = 0 ; Dbus = 32’h12345678 ;
#1 control = 1 ; Dbus = 32’hZ ;
#1 dout = 32’h55555555 ;
#1 control = 0 ; Dbus = 32’h87654321 ;
#1 $finish ;
end
endmodule
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CPU Data Bus Buffer Simulation
 Simulation results
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