Transcript Low Overhead Interrupt Handling with SMT

Low Overhead Interrupt
Handling with SMT
CS252 Spring 2005 – Final Presentation
Greg Gibeling
Andrew Schultz
5/10/2005
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Problem
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Traditional OS interrupt handling
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High latency context switch
Excessive data copies
High bandwidth devices I/O architecture
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Ethernet speed increasing faster than processor
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Existing Attempted Solutions
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1 Gb/s Ethernet faster than a standard architecture
10 Gb/s Ethernet becoming common
Interrupt coalescing – poor latency
TOEs – not well supported, application specific
Smart NICs – typically for special purpose (MPI)
Polling – Unreliable, machine dependant
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Observations
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Trend towards many hardware contexts
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Many contexts
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Intel now has HT standard in their cores
Multi-core chips starting to ship
Multiprocessor SOCs
Easier to partition
How do we take advantage?
Devoting one to interrupts wont reduce processing
Programming inertia slows changes
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Programmers use certain interfaces
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TOEs
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Solutions should not require massive changes
Major changes take forever to be adopted
Have been around for a while
Still don’t have wide-deployment
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Solution (1)
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SMT Hot Thread for Interrupts
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Accelerate Interrupt Handling
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Remove context switch overhead
Pin cache contents
Allow OS control
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Increase interrupt handler flexibility
Reduce hardware dependence (Smart NIC)
Use programmer intuition about program structure
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Zero Copy (future work)
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Very high level cache prefetch hints
Data is placed directly in user space
Does not require a large physical memory block
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Solution (2)
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SMT Hot Thread
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Reserved
One of many threads
SMT
Thread
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L1 Instruction
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N-way associative
Limited set pinning
Int
Thread
L1I
Based on LRU
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SMT
Thread
CPU
Cache Pinning
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L1D
L2
L1I
L1D
L2
Trace pinning
L2 Combined
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SMT
Thread
Range Pinning
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Memory
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Experimental Setup
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M5 Simulator
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Multiple full system simulation
Event driven memory system
Cycle accurate in-order or OoO
Our Parameters
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Current Pentium4 like system
Alpha ISA (EV6 211264)
Simple CPU model
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CPU
Multiple contexts to simulate
SMT
Full Memory Model
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L1I
Mem
L1D
L2
MemBus
South
Bridge
North
Bridge
B
(io)
NIC
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Benchmarks
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Netperf
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Basic UDP traffic flood
Simulates high network load, low CPU load
Netperf (w/NAT)
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Insert a NAT box between server and client
Simulates high network load, high CPU load
Client
Server
Client
NETPERF
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NAT
Server
NETPERF w/NAT
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Instrumentation
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Simple in-order SMT model
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Instrumented Linux kernel
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Create “bins” to measure statistics in different parts of the
OS (kernel, user, interrupt, tasklets)
Capture SMT thread to service interrupts and run NIC
related tasklets
Created “cache pinning” policy
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Lower potential pressure on memory system than aggressive
out-of-order model, but sufficient for measuring functional
memory access
Replaces basic LRU replacement policy
Pseudo-instructions explicitly pin data structures or turn on
trace pinning (in I or D cache)
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Instrumentation
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Metrics
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Cache Misses (L2/I/D)
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NetPerf bandwidth
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M5 allows binning, in order to separate misses
during the interrupt handler from other code
Measure impact of cache pinning
Application level performance
“What can this accomplish?”
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NETPERF Performance (1)
L2 Miss Rate
Bandwidth
0.02
900
0.018
800
0.016
700
0.014
Miss Rate
Uni
SMT
Ded
0.01
Bandwith (Mb/s)
600
0.012
500
Uni
SMT
Ded
400
0.008
300
0.006
200
0.004
100
0.002
0
0
No Pinning
128
32
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2
Cache Fraction Pinned
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No Pinning
128
32
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2
Cache Fraction Pinned
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NETPERF Performance (2)
DCache Miss Rate
0.016
0.04
0.014
0.035
0.012
0.03
0.01
0.025
Uni
SMT
Ded
0.008
Miss Rate
Miss Rate
ICache Miss Rate
0.006
0.015
0.004
0.01
0.002
0.005
0
0
No Pinning
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2
Cache Fraction Pinned
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Uni
SMT
Ded
0.02
No Pinning
128
32
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2
Cache Fraction Pinned
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NETPERF Results
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Bandwidth increase of 30%
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Dedicated SMT thread successful
Cache performance is even
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Cache Pinning
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L2 –
ICache DCache -
No Impact
Performance Hit
Performance Hit
This is an IO bound benchmark
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NATPERF Performance (1)
L2 Miss Rate
Bandwidth
0.012
2000
1800
0.01
1600
1400
Uni
SMT
Ded
0.006
Bandwidth (Mb/s)
Miss Rate
0.008
1200
Uni
SMT
Ded
1000
800
0.004
600
400
0.002
200
0
0
No Pinning
128
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2
Cache Fraction Pinned
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No Pinning
128
32
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2
Cache Fraction Pinned
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NATPERF Performance (2)
ICache Miss Rate
DCache Miss Rate
0.06
0.14
0.12
0.05
0.1
0.04
Miss Rate
Miss Rate
0.08
Uni
SMT
Ded
0.03
Uni
SMT
Ded
0.06
0.02
0.04
0.01
0.02
0
0
No Pinning
128
32
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2
Cache Fraction Pinned
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No Pinning
128
32
8
2
Cache Fraction Pinned
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NATPERF Results
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Bandwidth decrease
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All processing for NAT is handled in kernel
Dedicated thread is doing all the work
Cache performance improvement
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Cache Pinning
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L2 –
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30% improvement at ½ pinned
Note that this corresponds to bandwidth peak
ICache DCache -
Performance Hit
Performance Hit
Processing dependent benchmark
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Conclusions
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SMT Hot Thread
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Cache Pinning
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Definite success
Requires a multithreaded application
130% speed increase on NETPERF
Qualified Success
Helpful at the L2 level for NATPERF
Seemingly detrimental at L1
Deserves more testing
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Future Work (1)
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Processing Intensive Benchmark
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NETPERF
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NATPERF
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Single threaded
Doesn’t fully test an SMT system
SPECWeb99
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Excessively simple
Doesn’t include processing overhead
Died horribly on the M5 system
This might provide a better benchmark
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Future Work (2)
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Detailed profiling of memory usage
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Examine performance with OOO CPU model
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Determine optimal data structures/traces to pin
Ready, but would require massive sim time
Extend basic architecture
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Implement zero-copy protocol
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Comparisons
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5/10/2005
Preferably consistent with traditional interfaces
Click – Can this match polling performance
IDS/Packet Capture – Can this handle line speed
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Related Work
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Hardware
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Software (OS)
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U-Net – ADU + fewer copies, more application control
Click – Change method from interrupt to polling
Interrupt coalescing – Add latency, reduce thrashing
Commercial Products
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5/10/2005
EMP – True zero copy on NIC
SMT exception handling – Done for TLB misses
On-chip NICs – Tighter coupling between NIC and CPU
TOEs and accelerators – Shift processing to special devices
There are commercial products approaching this solution
Network Analyzers
IDS Systems
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