Transcript Document
itlDragon
circuit placement tool
Kirill Kornyakov January, 2007
About project
Since summer 2005 Team Meyerov Iosif Kirill Kornyakov Nina Kurina Artem Zhivoderov Email [email protected]
mentor team leader researcher researcher 2/7/2007 2 / 12
Project goals
Our team conducts a research on Very Large Scale Integration placement – a classical problem in IC physical design.
Aims of activity • Investigation of existing placement algorithms • Algorithm design and implementation • Innovative activity • Experiments, analysis and results publication 2/7/2007 3 / 12
Collaboration aspects
• Our research can contribute to Intel IC design tools development.
• Demonstration of Intel products efficiency and superiority (whitepaper publication, flash demo creation).
• Potential interest of third-party researchers dealing with VLSI CAD.
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Problem relevance
Placement is the key step in IC design.
Quality of placement determines: • Clock rate • Delay • Power consumption Wire length minimization is a traditional optimization objective.
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Problem setting
We solve the wirelenght-driven standard cell placement problem.
terminals cells rows sites 2/7/2007 6 / 12
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Placement flow
Recursive bisection Bin-based annealing Adjust Bins to Rows Cell annealing Remove overlaps, Local improvement 7 / 12
Milestones
Initial stage (July ’05 – Feb ’06) • VLSI placement field investigation • Skeleton of placer created First (pilot) stage (Feb ’06 – May ‘06) • First version of itlDragon released • Flash-demo created • Technical report written • Three papers published 2/7/2007 8 / 12
Milestones
Second stage (July ’06 – Oct ’06) • Second version of itlDragon released (with greatly improved quality) • Technical report written • One paper published 2/7/2007 9 / 12
Comparison of placers
mPL 6 itlDragon 2 Dragon 3 Capo 10 FengShui 5
0,0% 2,0% 4,0% 6,0% 8,0% Quality Lag (lower values are better) 10,0%
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Current activities
• Mixed-sized placement.
• Publications (algorithm enhancement and complexity analysis).
• Placer improvement.
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