Transcript Document

Cyclic-ADC developments
for Si calorimeter of ILC
Laurent ROYER,
on behalf of the MicRhAu designers collaboration
7th International Meeting on Front-End Electronics, Montauk NY – May 18th - 21st, 2009
"Pole" MicRhAu: collaboration for µelectronics
Laboratoire de Physique Corpusculaire
de Clermont Ferrand
Institut de Physique Nucléaire
de Lyon
MICro-electronic RHone AUvergne
Collaboration for µelectronic designs:
 12 µelectronic designers
 analog/mixed ASIC for physic experiments and applications (medical):
 Charge preamplifier
 Shaper, filter
 ADC
 OTA, drivers
 T&H
 Comparators
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
2
Projects @ MicRhAu
LHC
T2K
VFE for liquid argon TPC
LHCb: preshower
ALICE: dimuon trigger
CMS: preshower & Ecal
Taranis
Si detector for satellite
Etoile
S-CMS
Beam Hodoscop of PM
S-ATLAS
INNOTEP
Readout chip for PET
Under discussion …
STAR
Readout chip for DHcal
Readout chip for ECG sensor
Readout chip for SiW Ecal
ILC
Yesterday
Now
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
Tomorrow
3
ADC developments @ MicRhAu
Speed
Pipeline
8 bits – 100 MS/s
240 mW
100 MS/s
10 MS/s
Flash
6 bits * – 20 MS/s
1 mW
Pipeline
10 bits – 4 MS/s
35 mW
Flash
8 bits – 50 MS/s
60 mW
1 MS/s
* with missing code
at high dynamic range
Cyclic
12 bits – 0.15 MS/s
3.5 mW
0.1 MS/s
Wilkinson
12 bits – 0.0125 MS/s
2.9 mW
0.01 MS/s
6 bits
8 bits
10 bits
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
12 bits
Resolution
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ILC: challenges for Si-W Calorimeter

Sandwich structure of: thin wafers of silicon diodes
(~200 µm) & tungsten layers

High granularity : diode pad size of 5x5 mm2

High segmentation : ~30 layers

Large dynamic range (15 bits)

Low
POWER
is the
KEY issue
(CdlT)
0.1 MIP -> ~3 000 MIPS

Embedded Very Front End (VFE) electronics

Minimal cooling available

> 100.106 channels
 Ultra-low power : 25 µW per VFE channel
« Tracker electronics with
calorimetric performance »
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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VFE electronics of Si-W Ecal
channel n
C

Shaper
ADC
A
N
A
L
O
G T
SCA
1
AMPLI.
Charge
pre-amplifier
A
N
A
L
O
G
Shaper
10
filtered signal
Shaper
pre-amplified signal
Shaper
O
M
E
M
O
R
Y
–
12 bits
SCA
 12 bits with 2-gain shaping
Time of conversion: time budget of
500 µs to convert all data of all
triggered channels
– Ultra low power:
 2.5 µW/ch (10% of the VFE
power budget)
 Memory depth of 5  0.5 µW
per conversion
 Power pulsing needed
TRIGGER
channel n+1
Die area:
 as small as possible…
– Resolution:
–
D
I
G
I
T
A
L
Discri.
Fast
Main requirements for the ADC:
ADC
12 bits
Analog electronics busy
1ms (.5%)
A/D conv.
DAQ
.5ms (.25%)
.5ms (.25%)
IDLE MODE
198ms (99%)
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Single or multi-channel ADC ?
64-channel VFE chip
64-channel VFE chip
shaper 1
analog memory
analog memory
preamp
analog memory
shaper 10
analog memory
shaper 1
analog memory
preamp
12-bit ADC
shaper 1
analog memory
32 channels
....
....
shaper 10
shaper 10
analog memory
shaper 10
analog memory
shaper 1
shaper 1
analog memory
shaper 10
analog memory
shaper 1
analog memory
shaper 10
analog memory
preamp
preamp
analog memory
32 channels
shaper 10
shaper 1
n channels
shaper 1
analog memory
shaper 10
analog memory
analog memory
a
n
a
l
o
g
analog memory
shaper 10
12-bit ADC
12-bit ADC
a
n
a
l
o
g
analog memory
analog memory
analog memory
analog memory
M
U
X
preamp
preamp
12-bit ADC
analog memory
analog memory
preamp
preamp
analog memory
12-bit ADC
shaper 1
12-bit ADC
analog memory
preamp
shaper 10
12-bit ADC
Digital Data Bus
12-bit ADC
shaper 10
analog memory
preamp
preamp
12-bit ADC
analog memory
analog memory
Digital Data Bus
shaper 10
shaper 1
....
12-bit ADC
shaper 1
....
preamp
analog memory
....
analog memory
....
shaper 1
M
U
X
n channels
analog memory
analog memory
Digital electronics
Digital electronics
Single-channel ADC scenario
Multi-channel ADC scenario
With one-ADC-per-channel architecture:


Short analog sensitive wires from memory to ADC
A digital Data Bus far from sensitive analog signals
 Only ADCs of
triggered channels powered ON
 Conversions of channels done in parallel

Integrity of analog signals saved
Power saved
No "fast" ADC required
Pedestal dispersion of ADC "added" to the dispersion of the analog part
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
…. but calibrated
7
Conventional 2-stage Cyclic architecture
SC Networks
A1
Vin < -Vref ... +Vref >
A2
x2
+
x2
+
 one cycle 
DAC1
Vin
0
Vin
DAC2
Vin
b0
b0
DAC
-
A2
A1
MSB
MSB-1
Logic
Digital data
processing
+
b0
-Vref
0
Final output
 One cycle = two phases of amplification and sampling
 At each cycle (one clock period), 2 bits are delivered  MSB then MSB-1, …..until LSB
 For an n-bit ADC, n/2 cycles are required
 The key block: gain-2 amplifier (switched capacitors amplifier)
 The precision of the gain-2 amplification gives the precision of the ADC
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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1,5 bit/stage Cyclic architecture
SC Networks
Vin < -Vref ... +Vref >
x2
x2
+
DAC1
Vin
+
DAC2
Vin
b0, b1
b0, b1
2
Vref/4
DAC
-
Digital data
processing
+
Vin
2
Logic
+
-Vref/4
+Vref
-Vref
b0
b1
0
Final output
+ 1 redundant bit at each cycle
 Precision of the ADC becomes insensitive to the offset
of the comparators up to ± 1/8 of the dynamic range (± 125mV for 2 V)
 Number of comparators is doubled
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Enhanced architecture: "Flip-around amplifier "
SC Networks
Vin
x2
+
+
SC Networks
Vin
+
x2
A
DAC1
Vin
DAC2
Vin
b0, b1
DAC1
Vin
b0, b1
DAC2
Vin
b0, b1
2
Phase 1
+
A
b0, b1
2
D ig ita l d a ta
p ro c essin g
Phase 2
D ig ita l d a ta
p ro c essin g
 one cycle 
A
MSB
A
 A single amplifier shared by the two stages
 As main of the power is consumed by amplifier
 reduction of power up to 40%
MSB-1
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Enhanced architecture: "Flip-around amplifier "
PHASE 1
VTH_H
C2
Amplification
bit1_H
VTH_L
VREF1
clk+
VREF2
DAC
AMPLIFIER
bit1_L
C4
VTH_H
1 MHz clock
Sampling
VTH_L
clk-
"Start conversion " signal
DAC
Two phases of conversion with a single amplifier
PHASE 2
VTH_H
11
1 2 3
9
7
4
12
C2
5
Sampling
VTH_L
clk+
6
DAC
8
10
Output signal of the amplifier
Amplification
C4
VTH_H
bit2_H
VREF2
AMPLIFIER
VTH_L
clk-
DAC
VREF1
bit2_L
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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The cyclic ADC designed
 Clock frequency: 1MHz
 Supply voltage : 3.5V
Die area of the core = 0.175mm2
 Technology: 0.35 µm CMOS Austriamicrosystems (reliable and cheap !!)
 ADC designed with the validated building blocks (Amplifier & Comparator) of a 10-bit
pipeline ADC (published in IEEE NSS in June 08) but optimized for the 12-bit precision
requirement
 Power pulsing system implemented
 Digital process of the bits (1.5 bit/stage algorithm) performed by an external FPGA
 Fully differential ADC: analog signal, reference, clock…
"Fully-Differential Circuits have very good PSRR and cross-talk rejection" Michael K.
… and also a good rejection of common mode noise induced by digital electronics
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Comparator


Comparator
Fully differential latched architecture
Power consumption: 280µW


Measured performance
Sensitivity = input noise : < 280 µV (95% C.L.)
Offset: 20mV ± 9 mV (68 % C.L.)  far from the
± 125 mV tolerated by the 1.5bit/stage architecture
CLOCK
+3.5V
+3.5V
V+in-V+ref
Sw
OUT
V-in-V-ref
OUT
Latched comparator
Dynamic memory
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Amplifier




Amplifier
Fully differential and rail-to-rail
2 amplification stages
Resistive CMFB
Power consumption: 2870 µW
Capacitive load (feedback + sampling):
3 x 0.8pF
Requirement
@ 12 bits/1MHz
Performance
Open Loop
DC Gain
 16k
19.6k
Fc à -3dB
174 Hz
2,5 kHz
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Charge injection: Bottom plate sampling
S1 CF
S2
Vin
S1
 S1 remains ON, S2 turns OFF
•
•
Cs
Ground impedance smaller than1/j(CF+CS)
 charges mainly injected to the ground
Residual charge is constant and cancelled by differential structure of
the gain-2 amplifier
 S1 turn OFF, S2 remains OFF
•
Input (Vin) impedance smaller than 1/j(CP+CJ)
 charges mainly injected back to the input
Hardware delay introduced between
control signals of S1 & S2 gates
S1
CJ
CF
CP
Vin
S1
CJ
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
Cs
15
Measurement setup for ADC
Test Bench:
 Generic board for ADC tests
 Analogue signal generator: DAC 16 bits (DAC8830)
 PC/LabView Slow Control through USB interface
 Data processing with Scilab package
USB link
Chip under test
Static measurements :
 Input ADC signal: ramp from 0 to 2V
 > 4096 steps -- 50 measurements / step
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Power pulsing measurement
1 µs for recovery time included after power ON
Measurement of consumption with
duty cycle power ON/OFF
Master current sources
switched OFF
Integrated consumption
with ILC timing : 0.12 µW per conversion
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Measurements of the performance
Integral Non-Linearity
Differential Non-Linearity
 DNL<+/-1 LSB
 No missing code
 INL<+/-1 LSB
Standard deviation = 0.84 LSB (420µV)
Noise
But Yield ≈ 60%  designed of a new "process-hard" gain-2 amplifier
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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New designs
 4 new ADC with 4 new amplifiers designed and submitted to foundry in
March
 Reduction of power supply voltage: 3.5V to 3.0V and optimization
(reduction) of BW performance of the amplifier
 Improvement of the yield: reduction of biasing variation versus process
fluctuation  single stage amplifier
Layout of the chip submitted in March 09
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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New Amplifiers
+3V
CMFB
Io
Io
T7
M9
M10
M7
M8
T8
T3
T4
Out1
T5
Out1
VMC
T6
Out2
M5
VMC
M6
 Folded cascode structure
 Current CMFB (reduced
consumption)
Out2
VMC
+3V
M3
M4
Io
Io
M9
M10
M7
M8
+3V
Io
Vin1
T2
T1
M1
Vb0
M0
Io
T0
Vin2
M2
Out1
VMC
VMC
M5
M6
M3
M4
+3V
Io
 Folded cascode structure
 Voltage CMFB
Out2
Vb0
T0
Out1
Out1
Out2
Out2
T0
VMC
Vin1
M1
M2
Vin2
M0
Io
Out1
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
Out2
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New Amplifiers
+3V
CMFB
Io
Io
T7
T3
T4
Out1
T5
M9
M10
M7
M8
Out1
VMC
T6
Out2
VMC
M5
M6
M3
M4
 Boosted folded cascode
structure
 Voltage CMFB
Out2
VMC
+3V
Io
Vin1
T2
T1
Vb0
T0
M1
M2
Vin2
M0
Io
 Folded cascode structure
(different sizing of transistors)
 Voltage CMFB
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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New Amplifiers performance
Architecture
Folded cascode
Folded cascode
Boosted Folded cascode
CMFB
Voltage
Current
Voltage
DC Gain
23 k
23 k
22 k
Consum.
570 µW
450 µW
1470 µW
BW
436 Hz
318 Hz
1700 Hz
Folded cascode
Voltage
28 k
1020 µW
428 Hz
> 174Hz
required
Previous amplifier consumption: 2870 µW
Simulated INL of the 4 new ADC
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Summary
 Measured performance in accordance with Si-W ECAL VFE
requirements
 Time conversion = 7µs
 Consumption < 0.6µW per channel (analog memory depth of 5 and power
pulsing included)
 2.5% of the power budget of one VFE channel
 Linearity: DNL < +/1 LSB &
INL < +/-1 LSB
 Standard deviation of Noise < 0.9 LSB
 Improvement of consumption and of the yield expected with the design
of the new amplifiers  chips have to be tested (received last week)
 The acquired experience with this cyclic ADC can be exported to other
project and/or to faster pipeline architecture
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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Thank you for your attention !!
A cyclic "machine" ??
L.ROYER – FEE 09 @ Montauk – May 18-21, 2009
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