Transcript Document

A Test Bench for full characterization of
the DIALOG chip
S.Cadeddu1, V. De Leo1, C. Deplano1,2, A. Lai1
1INFN Cagliari Italy; 2Università di Cagliari Italy
LHCb experiment
We present a semi-automatic test system designed for the complete
characterization of the DIALOG integrated circuit (see IEEE TNS
2004 N18-6). The DTS (DIALOG Test System) checks all the chip
digital functionalities. It measures the DIALOG output channels
programmable time delay and width with 72 ps of resolution.
DIALOG threshold voltage outputs are measured with 0.6 mV of
resolution. The complete characterization of one chip takes 2minutes.
DIALOG is a fundamental building block in the front-end
electronics of the Muon Detector of the LCHb experiment. LHCb,
currently under construction at the CERN LHC, will study the CP
violation and B mesons rare decays. The role of the LHCb Muon Detector is to detect muons tracks
with high transverse momentum, as a signature of a B meson decay. This is a crucial information for
the LHCb first trigger level. The LHCb Muon Detector consists of 5 stations along the beam axis and
is based on 3-GEM detectors and MWPC.
The trigger processor performs its algorithms on a
binary space point information sent by the front-end
B
mm
INTERACTION
BX ID
DETECTION
electronics: 126k channels (PCH) are output from the
detector. The granularity needed by the trigger is
16000 CARIOCA
MUON CHAMBER (MWPC/3-GEM)
coarser (26k channels LCH) to minimize sustainable
8000 DIALOG
8PCH
8PCH
8PCH 8PCH
noise level and detection rate per channel. The LHCb
F/E board
F/E board
4000 SYNC
ASD
ASD
Bunch Crossing (BX) frequency is 40 MHz. To assign
SERVICE board
(on crates)
the correct BX identifier to each event, it is necessary to
DIALOG
8LCH
equalize all the different contributions to PCH signal
10m cabling
delays, before sending the information to the trigger.
(LVDS)
The main delay contributions are:
SYNC IC
• µ-chambers time distribution  25 ns (4 ns rms)
• Particle time of flight
• Different cables length
The DIALOG main tasks are to realize PCH reduction already at the front-end level and to make
possible a proper detector time alignment, channel by channel. Both these tasks are configurable to
allow different possible combinations, according to each physical channel position inside the detector.
In the Muon System there are 8000 DIALOG.
45
46
47
48
49
50
51
52
53
+ -
54
55
25 ns
25 ns
25 ns
ANALOG SHAPER DISCRIMINATOR
I2C
MASTER
DIALOG CUSTOM IC
LOW VOLTAGE
CONTROLS
DELAY AND WIDTH ADJUSTMENT
CALIBRATION PULSES
LOGICAL CHANNEL GENERATION
THRESHOLDS FOR ASD CHIPS
OFF DETECTOR ELECTRONICS
SYNCHRONIZATION
COUNTING ROOM
TIME (PHASE) MEASUREMENT
DATA TO DAQ
DATA FORMATTING
RECONSTRUCTION
DATA TO MUON TRIGGER
DIALOG
(DIagnostic time Adjustment and LOGics)
ON DETECTOR ELECTRONICS
ASD: CARIOCA CHIP
DTS (DIALOG Test System)
ROUTER BOARD
The need to characterize the DIALOG
circuits completely in a short time has
required designing a dedicate Test
System. The DTS is a portable system
composed by 3 custom PCB (the
ROUTER board, the DIALOG board
and the TDC board), one PC and a custom C
DIALOG BOARD
software. The DTS hardware is controlled by
the PC program via an I2C interface. DIALOG
is placed on the DIALOG board which has a
Zero Insertion Force socket to allow the change
of the device under test. All DIALOG input
signals are provided by the ROUTER board.
TDC BOARD
The DIALOG output LCH and pulse signals
are connected both to the ROUTER board, for
DIALOG digital functionalities test, and to the
TDC board for the time measurements of
signals delay and width.
Four commercial 12-bit ADC are mounted on
the DIALOG board to measure the 18 threshold levels with a resolution of 0.6 mV of
LSB. Each ADC can be independently configured and read by the PC via the I2C
interface. The I2C signals are provided by the ROUTER board. The ROUTER board
is used to interface DIALOG with the software program and contains the I2C registers
to generate the DIALOG PCH input signals and to capture the LCH outputs.
I2C signals
I2C MASTER
TEST ROUTINES
REPORT FILES
16 LVDS PCH
DIALOG input
I2C signals
Reset
8 LVDS LCH
DIALOG output
I2C signals
Common Start
Reset
The main board of the DTS is the TDC board which has 4 commercial TDC driven
by an FPGA. On the board there are 1 common start input signal and up to 32 stop
input signals, 8 for each TDC, which can be individually enabled and configured. To
allow both LVDS and LVTTL stop signals logics, 8 LVDS to LVTTL converters are
soldered on board. The time measurements can be done for a individually selectable
positive or negative edge of the common start and of the stop input signals. The
measurements are done in a time interval up to 94 µs starting from 40 ns after the
common start selected edge signal (72 ns of resolution). After each power-on the
FPGA can be accessed via I2C by the software program (69 8-bit registers). To test
one DIALOG, two TDC are used: one for the 8 LCH and the other for the 2 pulse
signals. Two kind of measurements were done:
DIALOG is developed in CMOS IBM 0.25 µm radiation tolerant technology. It is installed directly on
the Muon chambers on a printed circuit board named CARDIAC (CARioca and DIAlog Card). In
 Time DELAY: made on the stop inputs positive edge, to verify the programmable
each CARDIAC DIALOG is placed after two Amplifier Shaper Discriminator (ASD) chips, called
delays set on DIALOG for each LCH and pulse signal;
CARIOCA (Cern and RIO Current Amplifier). The
 Time WIDTH: made both on the positive and on the negative edge of the LCH signals
DIALOG
block
scheme
CARIOCA chip has 8 binary output, therefore
to verify the programmable width.
DIALOG has 16 PCH as input channels and has up to 8
LCH as output channels.
DIALOG integrates fundamental tools required for the
The characterization of DIALOG (at room
Muon chambers time alignment and monitoring and
CARIOCA threshold levels measurements temperature) is managed by a custom C
for the Muon Trigger operation. It also provide many
program and takes about 2 minutes. It consists
y
=
p
+
p
x
0
1
other features for system control and diagnostic.
of DIALOG power consumption measurement,
In the DIALOG block scheme all the different
test of digital functionalities and test of analog
functional blocks are showed. Following the processing
features. A sample of 480 DIALOG chips was
stages from input to output there are: the Input Block,
tested with the DTS, 21 of which were rejected
the Programmable Delayer and digital Shaper (ADCDNL V
- V
for power consumption (about 4 mA for 19 chips
DLL) Block, the Masking Block, the Logical Channels
V
and 1 A for 2 chips) and other 10 were rejected
generation Block. There are also the ASD Thresholds
DIALOG
CORE:
ADC-DLL
for digital procedure failure. 330 DIALOG of
Block and the Counters Block. All DIALOG
the remaining 449 are validated as “good”. For
2
configurable tools are writeable and readable by I C
each threshold level, the linearity curve and the
interface. The DIALOG features are:
Slope of thresholds fit
DNL are measured inside the full DAC range
1. Programmable input signals time adjustment:
(0255) in a few seconds. The maximum peak
(31 steps of ~ 1.6 ns @ 40 MHz) by an external
to peak voltage variation is 35 mV.
selection or an automatic calibration using a DLL
(settable period ~ 59 ns [17 MHz]÷ 21 ns [48 MHz]).
Measurements of time delay and width were
Typical max delay  50 ns;
done for each LCH at the DLL locking code (@
Max possible delay  120 ns (@ 17 MHz).
40 MHz) and for the DLL code 0 and 255. The
Differential Non Linearity (DNL) < ± 0.3 LSB.
Intercept of threshold fit
same type of delay measurements were done for
2. Programmable output signals width adjustment:
pulse signals also. All the time and the voltage
(8 steps of ~ 3.2 ns each @ 40 MHz).
Typical shaping  28 ns. DNL < ± 0.2 LSB.
measurements are stored in two report files and
DIALOG pinout
later processed with a dedicated software. These
3. Possibility to put a MASK on every input channel.
files are analyzed if the DIALOG power
4. Logical Channel generation according with the
DIALOG has 113 pin, a width of 3875 µm and
trigger granularity (OR2; OR4; OR8).
consumption is in a range of (150 ± 20) mA and
LCH outputs time measurements
a length of 4900 µm. The power consumption
if the digital functionalities test passes.
15 delay units of 1.6 ns each
5. Sixteen 24-bit rate counters to monitor PCH.
is about 150 mA at a bias voltage of 2.5 V.
Measurements of 449 DIALOG circuits
n
measured
n
calculated
10.Triple-voted and auto-corrected register for better
SEU (Single Event Upset) immunity, both
configuration and state machines.
gnd
vdd
vdd
CARIOCA
pulse
Scalers
core
8 LVDS
Logical
Channels
Pulse + Delay Lines
gnd
gnd
DLL
ADC
9 ASD
threshold
levels
gnd
gnd
8 LVDS
Physical
Channels
vdd
gnd
vdd
vdd
LVDS
ASDQ
pulse
DLL
ADC
vdd
8 LVDS
Physical
Channels
thresholds
thresholds
gnd
vdd
Scalers
9. I2C interface (93 registers) to configure all DIALOG
tools.
9 ASD
threshold
levels
gnd
8. 2 ASD pulse generation signals with programmable
time adjustment for ASD chips test.
vdd
Pulse + Delay Lines
7. Internal Pattern generation to test purposes.
LVDS I2C out
Address
CARIOCA
pulse
LVDS
ASDQ
pulse
31 delay units of 1.6 ns each
8 width units of 3.5 ns each
The measurements done allow the definition
of the DIALOG test procedure and the proper
analog performances sorting intervals, needed
for a safe selection of the DIALOG mass
production chips (about 12000 devices).
Analog Sorting Intervals
o 2 ASDQ levels operate in a (0  625) mV range
with an Rload = 1 kΩ;
Reset
vdd
vdd
gnd
o 16 CARIOCA levels operate in a (0.625  1.2) V
range with an Rload = 24 kΩ;
LVDS I2C in
gnd
6. 18 different threshold levels for ASD chips
discriminator. Each is programmable independently
using a DAC (2.2 mV of resolution) plus a linear
output driver:
DLL calibrated at nominal 40 MHz frequency
LSB
calculated