Transcript Programming of FPGA in LiCAS ADC For Continuous Data Readout

Programming of FPGA
in LiCAS ADC for
Continuous Data Readout
Week 3 Report
Jack Hickish
1
Progress Last Week
Successfully compiled new code for the FPGA to facilitate constant data
processing. Namely:
- Modified (simplified) data flow path
- Modified acquisition and read / write controls
2
Since then…
Simulation
- Check that external input changes between FFI and FSI mode as
desired
- Check that data out of FPGA has followed correct data path
- Check for correct (continuous) operation of FFI mode. (and verify that
FSI mode still functions correctly)
3
Obstacles to Simulation
Internal FIFO couldn’t
(wouldn’t) be simulated.
Data In
Sampling /
Manipulation of data
FSI
Operation
External FIFO
FFI Operation
Data channels into the
FIFO could be checked
– simulations suggest
data is being routed
successfully but cannot
verify altered read /
write controls for FIFO
Internal FIFO
RAM
Data Out
over USB
4
Other Simulation Results
- FPGA will acquire data continuously when in FFI mode and successfully
route data to FIFO
- FPGA will switch between FFI and FSI operation modes when an
external signal is applied (this signal has been integrated into the current
USB “DAQ” software)
- FPGA “Test” feature works in both modes of operation
5
Experimentation
Next stage is experimentation with an FPGA loaded with new program
- Input signal via a signal generator, monitored by oscilloscope
- Output signals analysed with “DAQ” software
- Internal signals monitored with “Chipscope” software
6
Results so far
Existing ADC board in FSI operation
7
Results so far
ADC board FPGA implemented with new code
Generated signal 1MHz sin wave, ~1V amplitude
Successes:
- Data is going in and coming out (both
FSI and FFI mode)
Failures:
- Output appears not to be a sign wave.
Possible causes: New USB control
software doesn’t graph properly.
Input is 1MHz, allowing for only 3 samples
per period.
8
Results so far
ADC board FPGA implemented with new code
Generated signal 800kHz sin wave, ~1V amplitude
Below 1MHz input sin wave
frequency, board only outputs
noise.
This happens in both FFI and
FSI mode, on both new and
original versions of DAQ
software and is dependent only
on signal generator frequency.
???
9
The week ahead
-
Fix DAQ graphing facility
Test low frequency sin wave input using
1) New FPGA code on a different board
2) Original code in current board
-
Use chipscope to check internal signals
- Fact that FFI and FSI mode both output signal suggests either
1) Both modes are routing data correctly
2) Signal to change between modes isn’t doing anything!
(software simulation suggests this isn’t the case)
-
Continuous operation
10