Transcript Fed Software Status

UA9 Telescope DAQ
J. Fulcher
Imperial College
16 July 2015
Jonathan Fulcher
DAQ Basics
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Based upon slice of CMS Tracker DAQ
~ 1/440 of Tracker DAQ
All subsystems used except:
FEC
 CCU rings
 FMM
 FRL
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These are replaced by:
Vi2c card to program the modules
 Simple electrical clock distribution
 Home cooked trigger card for trigger rules and
backpressure handling
 FedKit Slink readout
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16 July 2015
Jonathan Fulcher
First Test Beam
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VME readout
Trigger rate limited to 600 Hz
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Due to limitations in FED VME readout
Plan for September test
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S-Link readout
Expected trigger rate up to 10kHz
16 July 2015
Jonathan Fulcher
CMS Tracker Readout System
QuickTime™ and a
TIFF (LZW) decompressor
are needed to see this picture.
16 July 2015
Jonathan Fulcher
Control and Readout System
10 sensors
Telescope has 30 channels ~
7680 strips in 5 planes
60 APVs
30 Fibres
Vi2c
1 FED
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Jonathan Fulcher
Trigge
rTTCci
Full System Setup
TTS
Compact PCI
crate
FED crate
FE modules
DAQ PC
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FED
Vi2c
FED Kit
Jonathan Fulcher
i2c
FED 9U Board
•9U VME64x
•PCB 14 layers (incl 6 power & ground)
•~ 6 K components (smallest 0402) ; ~ 25 K tracks
•BGAs largest 676 pins @ 1 mm pitch
•96 ADC channels :
AD9218 Dual package 10 bit @ 40 MHz
Half Analogue circuitry on Secondary Side
JTAG Boundary Scan
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Jonathan Fulcher
FED Overview
Modularity
96 Tracker
Opto Fibres
CERN
OptoRx Analogue/Digital
9U VME64x Form Factor
9U VME64x
Modularity matches Opto Links
12
12
FE-FPGA
Cluster
Finder
12
25,000 Si strips / FED
JTAG
FPGA
Configuration
Compact Flash
1 FED in Total.
VME-FPGA
VME
Interface
Up to 8 x Front-End “modules”
BE-FPGA
Event Builder
12
TCS
OptoRx/Digitisation/Cluster Finding
Back-End module / Event Builder
TTC
TTCrx
12
Buffers
DAQ
Interface
12
VME module / Configuration
Power module
Other Interfaces:
12
Temp
Monitor
12
Power
DC-DC
TTC : Clk / L1 / BX
DAQ : Fast Readout Link
TCS : Busy & Throttle
Front-End Modules x 8
Double-sided board
16 July 2015
Xilinx
Virtex-II
FPGA
VME : Control & Monitoring
TCS : Trigger Control System
Jonathan Fulcher
JTAG : Test & Configuration
Delay x 24
FE x 8
Firmware and FPGAs Baseline of 4 FPGA Final Designs
working...
VME x 1
BE x 1
34 Xilinx Virtex II FPGAs
up to 2M equiv gates each
Delay FPGA: ADC Coarse and Fine Clock Skewing.
FE FPGA: Scope and Frame Finding modes.
BE FPGA: Event building, buffering and formatting.
VME FPGA: Controls and Slow Readout path.
16 July 2015
Jonathan Fulcher
S-LINK VME Transition Card
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Simple 6U board:
VME
Backplane
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Provides interface between
FED and Slink Transmitter
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Provides access to FED
Throttle signals
Slink
Transition
Card
FED
DAQ Slink
Transmitter
6U
Ethernet
Connector
16 July 2015
Jonathan Fulcher
Slink Data &
Control
Signals
FED Throttle
Signals
Optical Analogue Links
•Data from the Tracker Front-End is transferred over
analogue optical links.
•2 APV25 data frames per optical channel
•Analogue link gain is set to 1
•Handling of zero suppression off-detector allows
more flexibility for algorithm adjustment and common
mode subtraction handling
•30 links carry ~ 3 Mbytes / s each @10kHz
•Factor 100 gained in Zero Suppression
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Jonathan Fulcher
Example 2xAPV25
Multiplexed Data Frame
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600
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0
1
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Jonathan Fulcher
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Fed Data Handling
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Fed buffer interpreted by specialized c++
unpacker class within CMSSW
Runs with thorough checking or streamlined data
access modes
Full data integrity self check
Access to all data in header and payload
Completely integrated within CMSSW
16 July 2015
Jonathan Fulcher
Run Control
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User logs onto a webpage
Selects the configuration he wants to run
He instantiates that configuration, this then launches
all the web servers on the specified machines for that
configuration and loads all the XDAQ Applications
He is then in a position to use the run control to issue
the state transition commands to all the XDAQ
Applications in that configuration.
Once you start the config the FED is ready to take
data, it remains only for the triggers to arrive.
16 July 2015
Jonathan Fulcher
Data Handling in XDAQ
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Standard Filter Unit and Storage Manager from
CMS are used
Goniometer Control in XDAQ application
Data Analysis performed in CMSSW
Fast feedback from analysis to Gonio
Mark P will present more…
16 July 2015
Jonathan Fulcher