Transcript IPC DESIGNERS COUNCIL MANAGEMENT PRESENTATION

IPC
DESIGNERS COUNCIL
How can we help you
and your local Chapter
be successful?
Agenda
IPC History Overview
 Designers Council History
 Designer Training and Certification
 Chapter Activities
 Summit, Symposiums and
Conferences
 Future Plans

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IPC HISTORY
1957 - FOUNDED BY SIX INDEPENDENT
BOARD FABRICATORS
1958 - USERS/SUPPLIERS MADE MEMBERS
1966 - MEMBERSHIP OFFERED TO
COMPANIES OUTSIDE THE AMERICAS
1977 - IPC NAME CHANGED TO REFLECT
ELECTRONIC PACKAGING AND
PROGRAMMING
1986 - COOPERATIVE LIAISON WITH ANSI
1988 - COMMITTEE RESTRUCTURING
1991 - IPC DESIGNERS COUNCIL FOUNDED
3
IPC Present Status

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REGULAR MEMBERS
TECHNICAL LIAISON MEMBERS
GOVERNMENT MEMBERS
TOTAL IPC Members 2,500 +
TOTAL Designers Council Members 956 +
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Beginning of Designers Council
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Proposed and validated during
IPC-D-275 workshops in 1991
Over 900 individuals exposed to ideas
during 14 workshops
Part of IPC’s Long Range Mission
statement - 1990
Formation meeting held in Atlanta January, 1992
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Designers Council Structure
DESIGNERS COUNCIL
IPC
BOD
DESIGNERS COUNCIL
EXECUTIVE BOARD
DESIGNERS COUNCIL
EDUCATION COMMITTEE
GENERAL MEMBERS
INDIVIDUAL
CHAPTERS
INTERNATIONAL
AFFILIATIONS
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DESIGNERS COUNCIL
CHARTER SCOPE
“TO ENCOURAGE, FACILITATE,
COORDINATE AND PROMOTE THE
ORDERLY INTERCHANGE AND
INTEGRATION OF DESIGN CONCEPTS
CONCERNING PRINTED BOARD, PRINTED
BOARD ASSEMBLY, AND RELATED
TECHNOLOGIES THROUGH
COMMUNICATION, SEMINARS,
WORKSHOPS, LOCAL, NATIONAL AND
INTERNATIONAL CHAPTER
PROGRAMMING AND OTHER MEANS.”
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OBJECTIVES

PROMOTE AND DISSEMINATE
INFORMATION REGARDING CURRENT
ACTIVITIES AND NEW DEVELOPMENTS
IN DESIGN TECHNOLOGY.

ENCOURAGE AND DEVELOP
COORDINATED INPUT AND RESPONSE
TO EXISTING AND PROPOSED DESIGNRELATED STANDARDS AND
PUBLICATIONS.
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OBJECTIVES - CONT’D

ACHIEVE MAXIMUM INDUSTRY
AWARENESS OF DESIGN
STANDARDIZATION ISSUES IN PRINTED
BOARD, PRINTED BOARD ASSEMBLY
AND RELATED DESIGN
TECHNOLOGIES.

ENCOURAGE AND COORDINATE THE
COMPILATION OF DESIGN
INFORMATION INCLUDING EQUIPMENT,
EQUIPMENT CAPABILITY (TOOLS AND
TECHNOLOGIES) AND RELATED
INFORMATION.
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OBJECTIVES - CONT’D

INCREASE INDUSTRY AWARENESS
OF THE ROLE THAT THE PRINTED
BOARD DESIGNERS PLAY IN THE
PRODUCT DEVELOPMENT CYCLE.

ESTABLISH A FORMAL EDUCATION
STRUCTURE AND CERTIFICATION
PROGRAM TO ENSURE DESIGNER
COMPETENCY AND CONSISTENT
DESIGN STANDARDS.
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OBJECTIVES - CONT’D

STIMULATE COMMUNICATION
AMONG AND BETWEEN PRINTED
CIRCUIT BOARD DESIGNERS AND
OTHERS IN RELATED ENGINEERING
DISCIPLINES.
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Designers Council Networking
Local Programming – Chapter Based
 National Conferences – Summit and
the Designer Learning Symposiums
 Designer Education Programs
 IPC Standards and Services
 Designer Email Forum Interchange

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Internal Support Functions
Database Management
 Invoicing
 Website
 Conferences and Symposiums
 Designer Education Development
and Implementation
 Web Forum Monitoring
 Membership Promotion

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IPC Designers Council
Training and Certification
A program that uses industry design
standards to develop a training syllabus that
informs designers on the manufacturing
issues of Printed Boards and electronic
assemblies. (DFM and DFA).
Program Development
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Developed by the IPC Designers Council Educational Committee
Achieve maximum awareness of the DFM and DFA issues
Encourage the coordination of design standardization issues
Increase designer profile elevation process
Stimulate communication between and among designers
Initiate a set of training modules to cover basic and focused subjects
Core Module, Advanced Module, Hi-Speed, HDI, etc.
Training materials - Study Guide, Industry Standards, CD-ROM
Certification requires passing exam (104 multiple choice questions)
Program Status
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Two day training review followed by the two hour exam.
Almost 3000 Designers have been certified (CID)
Over 500 Designers have achieved their CID+
Trainings centers located in the US, Europe, (Scotland
Netherlands, Germany) and Australia (Melbourne,
Sydney)
• Over ten officially approved trainers
• Data base continuously evaluates scores and answers
• Focus modules being developed for 2007
The Designers Certification Program has been devised and
produced by the Education Committee of the IPC Designers Council.
Designer Certification – CID
Description & format – click here ----
Its purpose is
to give
designers, and
other PCB
professionals,
the opportunity
to gain a world
wide
recognised
qualification
based on good
practice that is
required to
design,
manufacture
and test PCB’s.
Advanced Designer
Certification
Part 1 CID+
Description & format ---click here ----
High Speed &
Impedance Control
Focus Module
Description & format ---click here ----
RF Design Principles
Focus Module
Description & format ---click here ----
Advanced Designer
Certification
Part 2 CID++
Description & format ---click here ----
EMI Design
Focus Module
Description & format ---click here ----
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Description & format
Based on the leading IPC standards for PCB design, IPC
Designer Certification reinforces the knowledge gained by
professionals over their many years of experience and
good working practices.
Designers purchase the Designer Certification Kit that
includes self-study materials and enrolment in a two-day
IPC Designer Certification Preparation workshop. All
Designer Certification testing is done at the workshop
location shortly after it concludes. Individuals who do not
feel prepared to take the test immediately after the
training may choose to keep their exam voucher and take
the test at a later date. The workshop training provides an
in-depth view of the principles contained in the
examination and is strongly recommended for anyone
interested in obtaining the certification.
Study Guide contents - click here ----
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Status of Training Modules
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Basic Module
 Live
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Advanced One Module
 Live
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in 1999, minor changes 2005
in 2002, minor changes 2005
High Speed, High Frequency
 Objectives
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complete, live in 2005
Electro Magnetic Interference (EMI)
 Objectives
complete, live in 2005
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Electronic Module Objectives
20
• Original Segmentation
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• Proposed Segmentation
To layout Principles
Layout
– Basics of (HiSp)/(EMI)
Electrical
– Electrical Requirements
Materials Included where needed – Board characteristics
Components
– Layout Principles
Assembly Requirements
– Components and Assy
Board Fabrication
– Performance Parameters
To Board
Board Physical
– Analysis and Verification
Documentation
– Documentation
Inspection/Testing
To Performance and Analysis
Reliability
Proposed Segmentation
is in order of lectures
Module Concept Comparison
DAY 1
(DAY AND DATE)
8:00 AM
REGISTRATION AND PRESESSION COFFEE BREAK
8:30 AM
INTRODUCTION TO DESIGNER CERTIFICATION
BASICS OF EMI
1.1 EMI-Definition & Requirements
EMI-Sources & Spectra
Interference Paths & Effects
Product Requirements: Emission & Susceptibility
Overview Tests & Limiting Values
1.2 RF/EMI- Currents
Common- & Differential Mode
Formation of Common Mode Currents
Detection/Measurement of CM Currents
Samples of CM Currents on PCB & Cables
1.3 Wave shape and Frequency (= HS-Module)
Sine Wave Description
Digital Pulses and Harmonics
Time Domain and Fourier Spectrum; Bandwidth
Clock Frequency vs. Switching Frequencies
1.4 Fundamentals of EM-Fields
Parasitic Antenna in Electronic Systems
Electromagnetic Fields
Static Electric & Magnetic Field
High frequency Fields: Near/Far Field
Refreshment Break
EMI Design Module Training
ELECTRICAL REQUIREMENTS
2.1 Basic Radiation Sources in Electronic Systems
Magnetic Dipole - Samples & Calculations
Electric Dipole - Samples & Calculations
Resonances on PCB
Dipole as Receiver Antenna
Frequency & Radiation Spectrum of Digital Signals
2.2 Coupling Mechanism between Circuits
(> Franzis-EMV)
Description of TEM-Lines
Capacitive Coupling - Counter Measures
Galvanic-Inductive Coupling - Counter Measures (> FED 8.2.6.1)
Wave Coupling - Counter Measures
2.3 Power System Design and Decoupling
(FED- 3.9.1.0 and 3.9.1.2)
Capacitor Selection and Decoupling (> FED 6.2.2.1) (also 5.1)
Transient Suppression
Use of Planes
Embedded Capacitance
2.4 RF- versus DC-Ground
(see also 3.2)
Return Path Variation
Ground Plane Stitching
Split Plane Impact
Power system Radiation; Fringing
Lunch
EMI Design Module Training
BOARD CHARACTERISTICS
3.1 Printed Circuit Boards in Principle
(> Martin O'Hara "PCBSTD.doc" )
PCB Terminology
Construction of a PCB
PCB Design Parameters
Multilayer Build (> Martin O'Hara "PCBHS.doc" Chap. 7.2 + 7.2.1)
3.2 PCB Layout for EMC Segmentation
(> Martin O'Hara "PCBSTD.doc" )
Decouple Local Supplies and IC's
Grounding Techniques
Order of Layout
Other Tracking Issues
3.3 Double-Sided Boards vs. Multilayer (to be checked against 2.3)
Power/GND supply (FED 8.2.3.2 + 3.9.2 ?)
Signal Return-Path
EMI by Reflection and Crosstalk
Controlled Impedance Effects (reflection control)
3.4 Impedance Controlled Boards
(see HS-Module 3.2; shortened)
Impedance Definition
Microstrip and Stripline
Power Supply Impedance
Radiation from Power System; Shielding
Refreshment Break
EMI Design Module Training
LAYOUT PRINCIPLES
4.1 Single- and Double-sided Boards (> Franzis' Book Chap.4/ FED 8.1.5 + 8.1.6.1)
Disturbance Currents and Paths
Layout of Signal- and Power nets
C-Blocking/Decoupling
Radiation from Power & Signal nets
Grounding to Periphery
4.2 EMI Avoidance Strategy with Multilayer
I/O Segmentation; Circuit Isolation
GND Plane Shielding
Layout Priority Order
Inductance Issues
4.3 IC and Passive Placement/ Circuit Segmentation
Connector and Filter Placement
Analog vs. Digital Layout
High/Low Speed Zones
Circuit Group Shields/Circuit Balance
4.4 Contacting of Filters & Ferrites (Periphery)
Capacitors (on Board)
EMI-Ferrites & Inductors
Varistors; Diodes; Gas Shunts
Filter Boxes; Placement & Contacting
4:30 PM QUESTIONS AND ANSWERS
5:00 PM ADJOURN
EMI Design Module Training
DAY 2
(DAY AND DATE)
8:00 AM
PRESESSION COFFEE BREAK
8:30 AM
RECAP OF FIRST DAY
COMPONENTS AND ASSEMBLY
5.1 Passive Components
( > Martin O'Hara "Passives.doc")
Packaging
Resistors
Capacitors
Inductors
Transformers
5.2 Active Components
( > Martin O'Hara "ICs.doc")
Logic Families Principles
Packaging Influence (BGA Layout Concepts?)
Digital Devices
Analog Devices
5.3 Connectors & Cabling
Pin Assignment
EMI-Connectors
Shielded Cable; Transfer Impedance
Cable Contacting
5.4 Housing & Mounting (Enclosure Design)
Shielding Principle
Materials and Coatings
Opening Sizes & Form
Design Rules
Refreshment Break
EMI Design Module Training
PERFORMANCE PARAMETERS
6.1 Drive Voltage Characteristics
Voltage Differences
Capacitive Charge Effects
Power Distribution
Decoupling Character
6.2 System vs. Board Ground
Difference Explanation
Grounding Principles
Shield Effects
Improvement Methods
6.3 Transient Suppression
ESD
EFT/Burst
Surge/Lightning
Voltage Surges/Drops
6.4 Costs, Availability, Lead time
Multilayer vs. 2 sided Boards
Influence Layer Count & Line-width
Filtering & Test Efforts
Time to Market
(proposal 2E1 DC-Group)
(proposal 2E5 DC-Group)
Lunch
EMI Design Module Training
ANALYSIS AND VERIFICATION
7.1 EMI Evaluation with SW-Tools (i.e. Expert System)
Screen Room Characterization
Transmission Signal Saturation
Power Supplements for Leakage Testing
Interpretation & Consequences
7.2 EMI Demands/Requirements - Tests
EMI/EMC - Standards
Test Structure; Emission & Susceptibility
Émission Tests (i.e. EN 55011 etc.)
Susceptibility Tests (IEC 1000-4-x)
7.3 EMI-Measurements
Test Equipment (Overview)
Emission Test Setups
Susceptibility Test Setups
Conformity Declaration
7.4 Assembly Analysis Verification (= HS-Module)
Arrangement of Components Influence
Test Circuits for Radiation Emanation
Embedded Passives Ringing
External Shields & Coating
(> Rainer)
Refreshment Break
EMI Design Module Training
(> Rainer)
DOCUMENTATION
8.1 General Documentation Practices
Fabrication Master Specification Techniques
Assembly Shielding Definition Requirements
Grounding Description and Verification
EMC Approvals and Labeling
8.2 EMI Restricting Materials & Tolerances
Description of Material Properties
Specification and Source Control Drawings
Application Sequence Parameters
Preparation and Test Method Specifications
8.3 Multilayer EMI / EMC Construction
Definition of Plane Location
Describing Purpose of Hole Guard Bands
Random Conductor Flooding Parameters
Specific EMI Prevention Stack-up Description
8.4 Board Topology Issues
Component Assembly Shielding Requirements
influence of Coatings and Soldermask
Assembly Sequencing to Facilitate Attachment
Surface Finish and Solder Joint Radiation
4:30 PM QUESTIONS AND ANSWERS
5:00 PM ADJOURN
EMI Design Module Training
Topic
Sections
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Basics
Electrical
Boards
Layout
Assembly
Perform.
Analysis
Docum.
Totals
Percent
Q&A?
10%
15%
10%
15%
10%
15%
15%
10%
100%
Beta X & Y
Q&A Need
X & Y Finals
Unique/Dupe
30 = (20/10)
45 = (30/15)
30 = (20/10)
45 = (30/15)
30 = (20/10)
45 = (30/15)
45 = (30/15)
30 = (20/10)
300=(200/100)
8/4 = 20
12/6 = 30
8/4 = 20
12/6 = 30
8/4 = 20
12/6 = 30
12/6 = 30
8/4 = 20
(80/40) = 200
160 + 40 = 200
Psychometric Analysis
Basics of High Speed – 30/20
Basics of EMI – 30/20
1.1 EMI – Definition and Requirements
1.1 High Speed Defined
Low and High Frequency Signals
Signal Rise Distance; Edge Rate
Critical Line Length – Rise-time Relationship
Skin Effect; Signal Attenuation
EMI Sources and Spectra
Interference Paths and Effects
Test Structure: Emission & susceptibility
Overview Tests and Limiting Values
7/4
1.2 Wave Shape and Frequency
7/4
1.2 RF/EMI Currents
Sine Wave Description
Digital Pulses and Harmonics
Time Domain & Fourier Spectrum; Bandwidth
Clock Frequency vs. Switching Frequencies
Common and Differential Mode
Formation of Common Mode Currents
Detection and Measurement of CM Currents
Samples of CM Currents on PCB and Cables
9/6
1.3 Impedance Definition
9/6
1.3 Wave Shape and Frequency
Line Impedance –Water model
DC- versus Impulse Current
Electrical Line Impedance; Lumped C,L
Power Supply Impedance; Requirements
Sine Wave Description
Digital Pulses and Harmonics
Time Domain & Fourier Spectrum; Bandwidth
Clock Frequency vs. Switching Frequencies
7/5
1.4 Transmission Line Definition
Duplicate HS 1.2
7/5
1.4 Fundamentals of EM-Fields
Signals on TEM-Lines; Differential Signals
Propagation Delay, Attenuation, Slew & skew
Reflections and Oscillations; Termination topic
Coupled Lines; Crosstalk
Parasitic Antenna in Electronic Systems
Electromagnetic Fields
Static Electric & Magnetic Field
High frequency Fields: Near/Far Field
7/5
Beta and Live Q & A Segmentation
7/5
Electrical Requirements – 45/30
2.1 Power System Implementation
Electrical Requirements – 45/30
2.1 Magnetic Dipole - Samples & Calculations
Distribution Path; Ground Bounce
Bypassing/Decoupling
2-sided Boards
Multilayer; Embedded Capacitor
Electric Dipole - Samples & Calculations
Resonances on PCB
Dipoles as Receiver Antenna
Digital Signal Frequency/Radiation Spectrum
11/7
2.2 Signal Transmission
11/7
2.2 Coupling Mechanism Between Circuits
RF Signal Return Current
Reflections and Oscillation
Topologies and Terminations
Crosstalk (Forward & Backward) & Control
Description of TEM-Lines
Capacitive Coupling - Counter Measures
Galvanic-Inductive Coupling - Center Measures
Wave Coupling - Counter Measures
12/8
12/8
2.3 Circuit Analysis
2.3 Power System Design and Decoupling
Timing Margin; Clock Skew
Loaded Line Characteristics & Timing
Branching Issues; Stubs
Layer Skipping
Capacitor Selection and Decoupling
Transient Suppression
Use of Planes
Embedded Capacitance
10/7
2.4 Differential Signaling
10/7
2.4 RF- versus DC-Ground
Routing Techniques
Terminations
Influence of Planes
Conductor Width & Spacing
Return Path Variation
Ground Plane Stitching
Split Plane Impact
Power System Radiation; Fringing
12/8
Beta and Live Q & A Segmentation
12/8
Board Characteristics – 30/20
Board Characteristics – 30/20
3.1 General PC Board Fabrication
3.1 Printed Circuit Boards in Principle
Standard Materials (Laminates & Prepregs)
Material Properties (DK, CTE, ...)
Copper Requirements; VLP Foils
Process Tolerances & Influence Analysis
PCB Terminology
Construction of a PCB
PCB Design Parameters
Multilayer Build
7/4
3.2 Board Impedance
7/4
3.2 PCB Layout for EMC Segmentation
Impedance Classes
Single Ended Layering (Microstrip & Stripline)
Differential Pairs
Power planes
Decouple Local Supplies and IC's
Grounding Techniques
Order of Layout
Other Tracking Issues
9/6
9/6
3.3 Multilayer Constructions
3.3 Two- sided Boards vs. Multilayer
4 Layer Structures
6 Layer Construction
8+ Layer Constructions
Layering Approaches
Power/GND supply
Signal Return-Path
EMI by Reflection and Crosstalk
Controlled Impedance Effects (reflection control)
7/5
3.4 HDI-/Microvia Constructions
7/5
3.4 Impedance Controlled Boards
Microstrip Constructions
Stripline Constructions
Dual-Stripline Constructions
Impedance Variations & Tolerances
Impedance Definition
Microstrip and Stripline
Power Supply Impedance
Radiation from Power System; Shielding
7/5
HS 3.2 shortened
Beta and Live Q & A Segmentation
7/5
Layout Principles – 45/30
Layout Principles – 45/30
4.1 PC Board Design Elements
4.1 One- and Two- Sided Boards
Optimum Impedance Value
Proper Trace Width & Spaces
Maximum Stub Lengths
Test Structure needed
Disturbance Currents and Paths
Layout of Signal- and Power nets
IC-Blocking/Decoupling
Radiation from Power & Signal nets
10/7
4.2 Component Placement & Split Planes
Grounding to Periphery
11/7
4.2 EMI Avoidance Strategy with Multilayer
Circuitry Analysis; Bus Structures
Split GND/VCC Planes
Component Side Distribution
Periphery & Connectors
I/O Segmentation; Circuit Isolation
GND Plane Shielding
Layout Priority Order
Inductance Issues
12/8
4.3 Vias & Via Chains
12/8
4.3 IC/Passive Placement/ Circuit Segmentation
Mechanical Properties
Capacitance & Inductance of Vias
Influence on the Line Impedance
Return-Current Flow
Connector and Filter Placement
Analog vs. Digital Layout
High/Low Speed Zones
Circuit Group Shields/Circuit Balance
11/7
4.4 Pre-layout Analysis (Line Simulation)
10/7
4.4 Filters & Ferrite Contacting (Periphery)
Layer Stacking Strategy
Timing, Clock Distribution
Termination Strategies; Noise Budgets
Preventive Crosstalk Analysis
Capacitors (on Board)
EMI-Ferrites & Inductors
Varistors; Diodes; Gas Shunts
Filter Boxes; Placement & Contacting
12/8
Beta and Live Q & A Segmentation
12/8
Components and Assembly – 30/20
5.1 Bypassing/Decoupling Capacitors
Components and Assembly – 30/20
5.1 Passive Components
Real Capacitors; Impedance vs. Frequency
Dielectric, ESR & Loss Tangent
Parallel Connection of Capacitors
Optimal on Board Contacting
Packaging
Resistors
Capacitors
Inductors
7/4
5.2 Component and Package Selection
Transformers
7/4
5.2 Active Components
Parasitic Package Inductance & Capacitance
Rise time, Slew rate, Noise margin, Driving Force
Fan-out Wiring Requirements & Stub Length
Embedded Passives, COB
Logic Family Principles
Packaging Influence (BGA Layout Concepts)
Digital Devices
Analog Devices
9/6
5.3 Connector Systems
9/6
5.3 Connectors & Cabling
Mutual Inductive Coupling & Parasitic Capacitance
High Speed Connectors
Estimating Crosstalk
Return-Current Path
Pin Assignment
EMI-Connectors
Shielded Cable
Transfer Impedance Cable Contacting
7/5
5.4 Ribbon Cables
7/5
5.4 Housing/Mounting (Enclosure Design)
Signal Propagation
Frequency Response
Cable Rise-time
Cable Crosstalk
Shielding Principle
Materials and Coatings
Opening Sizes & Form
Design Rules
7/5
Beta and Live Q & A Segmentation
7/5
Performance Parameters – 45/30
6.1 Concurrent Layout Analysis (Line & BD)
Performance Parameters – 45/30
6.1 Drive Voltage Characteristics
Component IBIS Models; Loads, Terminations
Timing/Delay/Skew Optimization
Crosstalk & Reflections Analysis
Power Distribution System: Integrity Analysis
Voltage Differences
Capacitive Charge Effects
Power Distribution
Decoupling Character
11/7
6.2 Optimum Layer Relationship
11/7
6.2 System vs. Board Ground
Signal Layer Distribution; Shielding Planes
Split Planes; Cutouts, Field Fringing
Crosstalk in GND Planes
Stack-up Balance, Producability
Difference Explanation
Grounding Principles
Shield Effects
Improvement Methods
12/8
6.3 Material Properties & Selection
12/8
6.3 Transient Suppression
High Speed Dielectric Material
RC-Foil vs. Reinforced Material
Copper Thickness vs. Line width
Thermal Management; Heat sinks
ESD
EFT/Burst
Surge/Lightning
Voltage Surges/Drops
10/7
6.4 Costs, Availability, Lead time
10/7
6.4 Costs, Availability, Lead time
Influence Layer Count & Line width
HDI/µVia vs. Conventional Boards
Intermixing High Frequency Materials
Back Drilling for Stub Removal
Influence Layer Count & Line width
Filtering & Test Efforts
Time to Market
Multilayer vs. 2 sided Boards
12/8
Beta and Live Q & A Segmentation
12/8
Analysis and Verification – 45/30
7.1 Post Layout Analysis (Board Simulation)
Analysis and Verification – 45/30
7.1 EMI Evaluation with SW-Tools
Power Integrity: Decoupling & Noise Margin
Signal Integrity: Crosstalk & Reflections
Constraint Driven Routing Analysis
Delay/Skew Situation
Screen Room Characterization
Transmission Signal Saturation
Power Supplements for Leakage Testing
Interpretation & Consequences
11/7
7.2 Signal Integrity Measurements
11/7
7.2 EMI Demands/Requirements - Tests
Defining Test Equipment
Performance Parameters
On-Board Measurements
Interpretation & Consequences
EMI/EMC - Standards
Test Structure; Emission & Susceptibility
Emission Tests (i.e. EN 55011 etc.)
Susceptibility Tests (IEC 1000-4-x)
12/8
7.3 Impedance Control Testing
12/8
7.3 EMI-Measurements
Test Setup Methods
Coupon Design and Placement
Testing Differential Pairs
On-Board Measurements
Test Equipment (Overview)
Emission Test Setups
Susceptibility Test Setups
Conformity Declaration
12/8
7.4 Assembly Analysis Verification
12/8
7.4 Assembly Analysis Verification
Registration Capability
Test points and Test Nets
Embedded Passives
External Shields & Coating
Arrangement of Components Influence
Test Circuits for Radiation Emanation
Embedded Passive Ringing
External Shields & Coating
10/7
similar to HS 7.4
Beta and Live Q & A Segmentation
10/7
Documentation – 30/20
Documentation – 30/20
8.1 General Documentation Practices
8.1 General Documentation Practices
Mixture of Electronic and Hard Copy Data
Re-procurement of “as- built” requirements
Configuration Management Strategy
Field Reports and Maintenance
Fabrication Master Specification Techniques
Assembly Shielding Definition Requirements
Grounding Description and Verification
EMC Approvals and Labeling
7/4
8.2 Materials/Impedance Tolerance
7/4
8.2 EMI Restricting Materials & Tolerances
Dielectric Parameter Descriptions
Performance Variation Maximum Allowance
Coupon Verification Strategy
Prototype/High Volume Description Controls
Description of Material Properties
Specification and Source Control Drawings
Application Sequence Parameters
Preparation and Test Method Specifications
9/6
8.3 Multilayer Construction
9/6
8.3 Multilayer EMI / EMC Construction
Single Lamination Criteria
Sequential, build-up Multilayer
Embedded Passive Description and Control
Exotic Material Influence/Definition
Definition of plane location
Describing purpose of hole guard bands
Random Conductor Flooding Parameters
Specific EMI Prevention Stack-up Description
7/5
8.4 Board Thickness Issues
7/5
8.4 Board Topology Issues
Limitation for Card Edge Conditions
Assembly Support and Housing Influence
Moisture Influence & Conformal Coating
Sequencing Mat’l, Fabrication, Assembly and Test
Component Assembly Shielding Requirements
Influence of Coatings and Soldermask
Assembly Sequencing to Facilitate Attachment
Surface Finish and Solder Joint Radiation
7/5
Beta and Live Q & A Segmentation
7/5
•
•
•
•
Thirty two objectives
Two forms of tests; X and Y
Three hundred questions in the Beta
Two hundred questions needed for exams
– X form 80 unique questions; 40 identical
– Y form 80 unique questions; 40 identical
• Applicants need to be CID minimum
• Can add initials to status on Business Card
– CID/H, CID/E, or CID/HE
– CID+/H, CID+/E or CID+/HE
New Structure Status Summary
CERTIFICATION TESTING

IPC ADMINISTERED
- IN CONJUNCTION WITH TWO-DAY
PREPARATION WORKSHOP
- WORKSHOPS SCHEDULED IN
ADVANCE

IMMEDIATE FEEDBACK
- SCORED AT TEST SITE
- AREA SPECIFIC DISCUSSION
- PASS/FAIL RESULTS
- CATEGORY ANALYSIS REPORT
40
Education Committee
 Volunteer
Group
- Independent Designers
- Board Manufacturers
- OEM Representatives
- Consultants
- Representatives from
Education Community
41
TRAINING CENTERS











PREMIER - UK
SCOTTISH ADVANCED MANUFACTURING
CENTRE (SAMC)
COLLIN COUNTY COMMUNITY COLLEGE
FERRARI TECHNICAL SERVICES
EPTAC
PALOMAR COLLEGE
PIEK – NETHERLANDS
ATTEC – AUSTRALIA
SMCBA – AUSTRALIA
SKAANNING QUALITY AND CERTIFICATION
FED – GERMANY
42
Chapter Activity
Effective Leadership
 Interesting meetings
 Establish a Program Committee
 Have a way for Local Networking
 Invite Popular Speakers
 Workshop Study Groups
 Fund Raising Events

43
Chapter Structure and Planning
Talk to past Officers/Presidents
 Pull a Chapter together

 Keep
focused
 Create the bylaws
 Keep action oriented
 Anticipate some friction
 Involve the group
44
Constructive Planning





Goals and strategies
Don’t do it alone
Make the most out of meetings
Expect long-term effort
Money is important
45
Introduction to Fundraising
Think outside the work place
 Use the communities around
you.
 Choose the right fundraisers
 Make the basic decisions
 Plan the event
 Provide the extra’s
 Promote effectively

46
Fundraising Ideas
Auctions
Tournaments
Dinners
Roast &
Toast
Card
Parties
Flea
Market
Movie
Benefit
Vendor
Demo Day
Holiday
Themes
Seminars
Raffles
Tours
47
LOCAL CHAPTERS













ATLANTA
AUSTIN – HEART OF TEXAS
CASCADE (WA)
CHESAPEAKE
COLORADO
GATEWAY (MO)
GREATER BOSTON
GREATER OHIO
GREATER PHOENIX
HOUSTON
LONG ISLAND, NY
LOS ANGELES, CA
MIDWEST (MINNEAPOLIS, MN)
48
LOCAL CHAPTERS - CONT’D













NORTH TEXAS (DALLAS)
NORTHEAST OHIO
NORTHERN ILLINOIS
ORANGE COUNTY (CA)
PACIFIC NORTHWEST (OR)
RESEARCH TRIANGLE PARK (NC)
SAN DIEGO
SILICON VALLEY (CA)
SMOKY MOUNTAIN (TN)
SOUTHEAST MICHIGAN
SOUTHERN NEW ENGLAND (CT)
SPACE COAST (FL)
SUSQUEHANNA (NY)
49
INTERNATIONAL CHAPTERS






AUSTRALIA
GERMANY (FED)
CANADA
- MONTREAL
- OTTAWA
- TORONTO
UNITED KINGDOM
IRELAND (in process)
INDIA (IPCA)
50
DOMESTIC UNIVERSITY
PARTNERS
PALOMAR COMMUNITY COLLEGE
 COLLIN COUNTY COMMUNITY
COLLEGE
 LAKE WASHINGTON TECHNICAL
COLLEGE
 NORTH SEATTLE COMMUNITY
COLLEGE

51
Participation in Standards
Assign a chapter guru to the
design tool kit.
 Highlight chapter member
interests
 Incorporate a library function at
meetings
 Do book (Standard) reports
 Make each event a value add

52
SUMMIT, SYMPOSIUMS AND
CONFERENCES

Designers Summit – February 17-22, 2007 in Los
Angeles, CA






Designers Day
Designers Certification
Education
Networking
Exhibition
Designer Learning Symposiums –
Regional, Throughout the Year



Education
Certification
Networking
53
Path Forward for
IPC Designers Council Chapters

Monthly Local Chapter
Networking

Quarterly Teleconferences
54
Designers Council Future
Activities in 2007

Designers Summit – February 17-22
 Designers Day – Monday, February 19
 Certification Workshops – Sunday, Feb. 18
and Thursday, Feb. 22
 Technical Conference – Tuesday, Feb. 20
 Face to Face Designer Council Leadership
Breakfast – Tuesday, Feb. 20
 Standards Development Meetings
 Free Forums
 Exhibitions
 “It’s Your Party” featuring The Designers
Den – Wednesday, Feb. 21
55
Designers Council Future
Activities in 2007

Designers Day – February 19th
 Learn the latest in high speed design, the
lead free initiative, EMI and much more.
 Hear from experts about ways to prepare for
the future.
 Get the latest news on upcoming IPC
Designers Council programs and plans.
 Network with your peers.
 Attend the Designers Day Dinner.
56
Designers Council Future
Activities in 2007

Designers Learning Symposiums
May 22 – Bannockburn, IL
 August 15 – Toronto, Canada
 More to be announced


Release of Focus Modules for the
Designer Certification Program



High Speed
EMI
Updates to Basic and Advanced
Designer Certification Programs
57