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RETICLE ENHANCEMENT TECHNOLOGY
IN THE SUBWAVELENGTH ERA
IMPLICATIONS FOR DESIGN TO SILICON
• Design CD << Wavelength
• Variants of RET Pervasively Increasing
• Design Size Is Explosive
• GDS is an Inadequate PD Data Format
Consequently:
• Mask Data Prep Resources Are a Big Cost Adder
• PD to Si Equivalence Verification is A Major Issue
• Mask Manufacturability Drives Cost/Cycle Time Issues
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Subwavelength RET: An Increasingly Important Post Tapeout Flow
Behavioral & Logic Synthesis
Formal & Func. Verification
Phase Shift
Complient
Rules
DFT, DFM, DFD, DFR
Library Creation
Floorplanning , Place&Route
Noise, Power, Delay Extraction
Layout , Parasitics
A (GDSII)
Phase Shift
Methodology
MaskPrep
OPC
Tile
Mask Data
Reticle Mfg
Reticle
Litho Process
Si Process
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Si IC
B (Post-RET
GDSII)
RET Mini-Review
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Motorola Digital & RF Systems Roadmaps for Gate
Length Extend Below Native Stepper Resolution
Industry
Roadmap
Motorola
Roadmap
Stepper Wavelength
Chart Courtesy of Numerical Technologies, Inc.
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Summary - Reticle Enhancement Technology
Optical Proximity Correction (OPC)
Add shapes to design data (GDS II)
Corrects for litho optics & process
Rule based OPC - one mode fits all
Model-based OPC - customized to shape neighborhood
Phase-Shift
“Strong” PSM - Phase mask + binary (“cut”) mask
Used for gate printing CD, sheet rho, control
“Weak” PSM - Via clear areas include attenuator
Tiling
Rule based tiling - Doesn’t guarantee global planarity
Model-based tiling - POR for future reticles
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
OPTICAL PROXIMITY CORRECTION IMPROVES PRINTING
(ADDS SHAPES TO MASK)
MASK
WAFER
No
OPC
With
OPC
Photo downloaded from MicroUnity
(now ASML MaskTools) web site
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Rule-Based OPC
Fig.
1A
Fig.
1B
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Phase-Shifting
• Uses phase-modulation at the
mask level to further the
resolution capabilities of
optical lithography
Mask
180 o
phase-shifter
• Benefits:
– Smaller feature sizes
– Improved yield (process
latitude)
– Dramatically extended useful
life of current equipment
– Performance Boost
– Chip Area/Cost Advantage
for Embedded Systems
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
0.11mm
Printed using a ~0.18 mm nominal process
Phase Shift - Simple Idea, Complex EDA Challenge
Chrome Etch
Routing poly
(phase plate)
Legend:
Grey=
Opaque
Color=
Clear
180 Phase Etch
(phase plate)
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Gate
Binary
Mask
Clear
Area
Rule-Based Tiling
+

• Done with Boolean operations
• Only density of the template is variable
• Not adequate for arbitrary design
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Model-Based Tiling
• Different amount of tiles at different locations
• Uses Linear Programming and in-house software
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Model-Based Tiling - Large Manuafacturability Enhancement
Untiled reticle (768A)
(unmanufacturable)
Conventional
Rule-Based Tiling (702A)
(9% uniformity improvement)
193 nm ASML Stepper N.A. = 0.85!!!
Model-Based Tiling (152A)
(80% uniformity improvement)
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
RET is Increasingly Driving New Issues
Design Release Data Prep Resources
• Computation Time
• CPU Time
• Storage Requirements
PD to Si Equivalence Verification
• Design Changes AFTER DRC/LVS/Timing/Power
Mask Manufacturability
• Mask Fabrication Cycle Time & Cost
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
RET Methods Pervasively Expand as Technology Nodes Evolve
“Prototypical” Scenario
0.25 um
0.18 um
0.13 um
0.10 um
0.07 um
Rule-based OPC
Model-based OPC
Scattering Bars
AA-PSM
Number Of Layers Increases / Generation
Weak PSM
Rule-based Tiling
Optimization-driven MB Tiling
248 nm
248/193 nm
ISPD 2001 - Resources, Verification
193 nm
W. Grobman Mask Making
Main Drivers of RET Issues
0.25 um
0.18 um
0.13 um
0.10 um
0.07 um
Rule-based OPC
Model-based OPC
Data File Size, Computation Time, Mask Mfgbility
Scattering Bars
AA-PSM
Design Constraints, Mask Mfgbility, Mfg Complexity
Weak PSM
Rule-based Tiling
Optimization-driven MB Tiling
Computation Time, File Size, Timing/Power Reverification
248 nm
248/193 nm
ISPD 2001 - Resources, Verification
193 nm
W. Grobman Mask Making
RET
RESOURCES
BLOAT
Mask Data
Prep Resources Driven by
RET
(1997=1)
1000
1000
Data Size/
Level
Hours/design
100
100
Resources
# CPU’s
Data Size/Layer
# RET Layers
# CPU's
# Layers
Hours
Gate Mask Production (Days)
10
10
Mask
Production
(Days)
11
1997
1997
1998
1998
1999
1999
Year
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
2000
2000
2001
2001
(Est.)
Mask / Si Dimensions
(Source: ITRS)
1000
MPU Lpoly (nm)
Dimension (nm)
Mask Min. Image
Mask OPC Feature
200
100
50
10
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Year
Mask Metrology Dimensions for RET Implementation
Are Significantly Smaller than Predicted by ITRS Roadmaps
1000
MPU Lpoly (nm)
Dimension (nm)
Mask Min. Image
Mask OPC Feature
200
100
ITRS
Mask
Min. Feature
Assumption
50
RET-Driven
Mask
Min. Feature
10
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Year
Solutions
• Reticle Delivery Cycle
- Model-Driven Mask Inspection
• PD to Si Integrity
- Model Si AND Mask Process
- Use to Drive Si vs. PD Virtual Validation
• Intelligent OPC
- ID Critical Design Features
- Apply MB-OPC With Discrimination
• Use Parallel Processing
- Recapture Hierarchy For Compaction
and Functional Validation (e.g. Timing)
• Retain Design Data in PD Representation
- GDS Replacement Open Standard
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
RETICLE INSPECTION ISSUES






Defectivity is the most serious problem affecting reticle delivery
More acute with the introduction of OPC
OPC features do not resolve as drawn in the design on reticle
When inspected, OPC results in vast numbers of false defect detections
Worst case (currently typical), the mask cannot be inspected at all
Standard practice:
 De-sense reticle inspection tool so partially resolved OPC shapes do not cause
errors
 De-sensing for OPC also de-senses the tool to legitimate defects
Original Data with Serifs
Reticle Image on
Inspection Tool
From Kling, Lucas Motorola Patent
Overlay of sample design data (red),
OPC data (yellow), and reticle image
on inspection tool (white)
OPC RETICLE INSPECTION INNOVATIONS
 Create a data set separate from the design to mimic shrinkage and rounding of
OPC structures on reticle
 The only change from written data is that OPC structures are altered for
inspectability
 The altered data set is presented to the inspection tool
 Essentially we are inspecting to an image that depicts the reticle as it is
expected to appear after exposure transformations and chemical processing
Original data with serifs
Data with inspection shapes
From Kling, Lucas Motorola Patent
Database image with inspection
shapes on inspection tool
Reticle image on
inspection tool
RET Must Incorporate Virtual Stepper AND
Virtual Maskwriter
PD
No
OPC
With
OPC
With
Mask-Model
Based
OPC
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
MASK
WAFER
Si ~ Layout - Separate Mask and Wafer Process Models
Improve Manufacturability / Flexibility
Layout to Si
Common Today
MASK process
model
Courtesy: Numerical Technologies, Inc.
= This Paper’s Suggested strategy
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Improve Mask Inspection
Fix Linearity Bias (Small
vs. large feature)
(Esp. bad at metal: xtalk,
intralevel shorts… )
Fix E-beam writer artifacts
Model-Driven (MD) RET
- MD Data Processing
- MD Verification
Phase Shift
Complient
Rules
Behavioral & Logic Synthesis
Formal & Func. Verification
DFT, DFM, DFD, DFR
Library Creation
Floorplanning , Place&Route
Noise, Power, Delay Extraction
Layout , Parasitics
A (GDSII)
Phase Shift
Methodology
MaskPrep
OPC
Tile
Mask Data
Reticle Mfg
Reticle
MODELS
Litho Process
Si Process
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Si IC
B (Post-RET
GDSII)
Proper Models -> Local Design Integrity
Identify Critical Design Features
Apply OPC With Discrimination & Verify Si=PD
Layout with OPC
OPC Verification
Wafer Image Simulation
Printed Wafer
Courtesy: Numerical Technologies
Intelligent MB-OPC is Desirable
Add Vertices Only for Manufacturability
e.g. Apply OPC With Discrimination
44 Vertices
Today
Critical Requires MBOPC
Better
20 Vertices
Simply Must
Avoid Pullback
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Partitioning for Parallel Processing
Use Hierarchy (Library Cells)
AND/OR
Flatten and use explicit proximity effect range
(Global Wire / Custom)
Calculate OPC In Here
Keep Solution in Here
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
PROCESSING THROUGHPUT AND COST
RET
Today’s Model
N-Way Processor
Shared Memory
Full-chip
Hours -> Days / Run
~ $500K System
Not Easily Scaleable
Conventional License Model
Cluster
N Linux Nodes
Distributed Memory
Loose Multithreading (Optical / EM Effects
are Short Range Compared to
Compute Cell Size)
Hours / Run
~ N X $2000 System
Simple to Scale
--> Need New License Model
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Storage / Data Transmission “Explosion”
It’s Desirable to Compress Data Post RET
MB-OPC Breaks Hierarchy
Recapture Hierarchy by One or Both of:
1. Hierarchical Data Incorporated in Design Shapes
• GDS Is an Interchange Format
• Need Representation which Couples Physical with Other Design
Attributes
• Examples: SI2 Open Library API, Cadence Genesis
2. Use Pattern Extraction Heuristics to Identify Arrays of Shapes
• Can be Computationally Very Efficient - O(N) CPU time where N is the
Number of Shapes
• Available Now - Here’s a Quick Demo
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Example: Pattern Extraction Heuristic to Regain Hierarchy
Start With Flat Data File of Sequential Records,
Sort to Get Contiguous Records Of Same Shape, Different x,y Positions
opcode1
x
y
Shape Attributes
opcode1
x
y
Shape Attributes
opcode1
x
y
Shape Attributes
.
.
.
.
Opcode-k
x
y
Shape Attributes
Opcode-k
x
y
Shape Attributes
Opcode-k
x
y
Shape Attributes
Opcode-k
x
y
Shape Attributes
Opcode-L
x
y
Shape Attributes
Opcode-L
x
y
Shape Attributes
ISPD 2001 - Resources, Verification
Sort1
W. Grobman Mask Making
Sort2
Example: Pattern Extraction Heuristic to Regain Hierarchy
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
2000 Random Points + 9 X 7 Array
Example: Pattern Extraction Heuristic to Regain Hierarchy
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
After 1 Pass of Heuristic
Example: Pattern Extraction Heuristic to Regain Hierarchy
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
After Second Pass of Heuristic
Post-Parallel Processing Compaction and Verification
• Pattern Recognition Heuristics Can Be Very Effective for
Compaction
• This is Important for Efficient Data Delivery to Mask Shop
BUT
• Timing, Power, … Checking for Tiled Design Requires An
Even Better Connection of PD Data to Design
• Global Nets May Need Timing Verification after Tiling
• Consequently, RET Could Drive Industry to More Quickly
Adopt a New Standard Useful for PD Re-Timing After RET
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Open Library API (OLA) - SI2
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Example RET Design Flow Scenario
Workstation
Hierarchical
PD
Hierarchical
PD
Rule-based OPC
c:PSM
Si vs PD
(mask and litho
models)
Flatten &
Partition
•Smart MB-OPC
•Tiling
Partitioned Flat PD for Parallel Computation
(OLA-like PD Data Representation)
Parallel
Processors
Timing/Power Verify
Data Compaction
Mask Data
ISPD 2001 - Resources, Verification
W. Grobman Mask Making
Mask Inspect Data
Create Mask Inspect Data
Robust, Implementable RET Design Requires New Paradigms
• RET Requires Models of New Types - Closer to Fabrication
• Accurate PD -> Mask -> Si Models
•Drive Design Reverification
•Drive Mask Inspect Data for Mask Cycle Reduction
• Parallel Computation Can Shrink Compute Resources
• Recapture of Hierarchy Shrinks Data Size
• Recapture of Design Structure Drives Global Timing Verification
ISPD 2001 - Resources, Verification
W. Grobman Mask Making