Transcript Document

1
Critical Dimension Control and its
Implications in IC Performance
Costas J. Spanos
FLCC, 10/23/06
7/17/2015
BCAM
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Critical Dimension in Perspective
(Leff in particular)
• Controls both leakage and saturation current
• Depends on Litho, Etch, Implant, Diffusion, Annealing
• Its components can be measured with limited precision:
– CD SEM: 1-2nm
– Ellipsometry: ~0.5nm
– Electrical: ~0.2nm
• Has “hierarchical” nature with different variation mechanisms
–
–
–
–
–
Wafer to wafer
Across wafer
Across field, in 100’s of mm distances
Feature to feature, due to pattern density, etc.
Line edge roughness in 10’s of nm distances
• Industry strives to keep TOTAL variability under 10%. This means 3
sigma total of less than 1nm in the next couple years.
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Outline
•
•
•
•
CD Control
CD Modeling
IC Performance Impact
New Directions
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Some of the recent advances in CD Control come from added
Process Visibility – PEB, for example
Uniformity Control
Transient heating and cooling
Courtesy OnWafer Technologies
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PEB Temp Control Using Wireless Metrology
using multi-zone plate modeling and feedback
After
Before
Target = 120oC
2.700oC
0.175oC
16 plates, 120 ºC Target
Courtesy OnWafer Technologies
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Post Exposure bake Driven CDU Improvement
3.5
3
2.5
2
1.5
1
Process of Record
0.5
Optimize Temperature
0
Across
Plate
Optimize CD
Plate to
Plate
Courtesy OnWafer Technologies
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We can also monitor Plasma Etch Temperature…
Reduced He
Routine He
main
etch
pre-etch
over etch
de-chuck
Courtesy OnWafer Technologies
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Present Status of “Active” CD Control
Exposure
Etch
PA
Bake
PEB
Etch
Spin
HMDS
Poly Etch
System Etch
Photoresist
Removal
Develop
PD
Bake
ADI
AEI
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ELM
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On-wafer and in-line metrology in pattern transfer
I (x, y)
T (t, x, y)
V (t, x, y)
E (t, x, y)
…
Exposure
T (t, x, y)
PA
Bake
PEB
Etch
Etch
Poly Etch
System Etch
Photoresist
Removal
Thin Film
Develop
Spin
OCD
OCD
PD
Bake
HMDS
OCD
ELM
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CDU control has to incorporate many strategies
I (x, y)
Optimal Pattern Design
Exposure
PA
Bake
T (t, x, y)
FF control
PEB
Etch
Thin Film
FB/FF ControlDevelop
Spin
PD
Bake
Etch
T (t, x, y)
V (t, x, y)
E (t, x, y)
FF/FB Control, chuck diagnostics
Poly Etch
System Etch
OCD
FB Control
Photoresist
Removal
OCD
FB/FF Control
HMDS
OCD
Profile Inversion
FB Control
ELM
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Experiments
Joint TSMC, UCB, OnWafer Paper, SPIE 2004
Various PEB plate parameters determine behavior in each segment. These
parameters were varied and CD data was collected at the same time
Dynamic Profile V.S. CD – 9 factors
Overshoot mean
Overshoot range
Steady state mean
Steady state range
Steady state duration
Heating rate mean
Heating rate range
Cooling mean
Cooling range
• 9 thermal-related factors are extracted and linked to CD maps.
• Regression analysis is performed to establish statistical significance.
Feb. 2004 P. ‹#›
Joint TSMC, UCB, OnWafer Paper, SPIE 2004
Within Lot CDU Summary
Wafer to
Wafer
4 PHP/ 4DEV
CDU
CD Mean
Baseline
0.01
0.099
0.009
0.098
CD range CD range
=3.4nm 3.4nm
0.008
Baseline
0.097
0.094
0.004
0.093
0.003
0.002
0.001
0
1
2
3
4
5
6
7
8
Across Wafer
CDU =3.8nm
9
10
11
12
13
0.092
0.091
0.09
14
PHP compensated
15
16
17
18
19
20
CD range
1.5nm
CDU
CD mean
0.01
0.099
0.009
0.098
0.008
0.097
0.007
CDU
Adjusted
0.096
0.006
0.095
0.005
0.094
0.004
20 Wafers
0.093
0.003
0.092
0.002
CDU=3.5nm
0.001
0
1
2
3
4
5
6
7
8
9
10
11
12
0.091
0.09
13
14
PHP re-compensated
15
16
17
18
19
20
CDU
CD mean
0.010
2nd
CDU
25 Wafers
0.103
0.102
0.008
0.101
0.100
0.006
0.099
0.005
0.098
0.004
0.097
0.003
0.002
0.096
CDU=3.5nm
0.001
0.095
0.000
0.094
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
• Dramatic CDU improvement was achieved with TCM
Feb. 2004 P. ‹#›
CD range
1.0nm
0.009
0.007
iteration
CD mean
0.095
0.005
CD mean
20 Wafers
0.096
0.006
24
CD mean
CDU
0.007
13
Supervisory Control with Wireless Metrology
Example chip speed map
• Across-wafer (AW) CD (gate-length) uniformity impacts IC
performance
– Large AW CDV
low yield
large chip-to-chip performance variation
• How to cope with increasing AW CD variation?
– Employ design tricks, e.g., adaptive body biasing, which has limitations
– Reduce AW CD variation during manufacturing is the most effective
approach
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CD Uniformity Control Approach
•
Making each process step spatial uniform
is prohibitively expensive
•
Our approach: manipulate PEB
temperature spatial distribution of multizone bake plate (and die-to-die dose) to
compensate for other systematic acrosswafer CD variation sources
CDU Control Framework
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Multi-zone PEB Bake Plate
6
5
3
Approximate schematic setup of
multi-zone bake plate
1
Each zone is given an individual
steady state target temperature,
by adjusting an offset value
2
7
T=Ttarget-Offset+effect of other
zones
4

Zone offset
O
knobs
PEB Bake
Plate
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
 T ( x, y )

 CD( x, y)
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Develop Inspection (DI) CDU
Control Methodology II
• DI CD is a function of zone offsets
Temperature
Offset Model
 T1   g 1 O1 , O 2 ...O7  

T   ...   
...

Tm   g m O1 , O 2 ...O7 




CD DI

 T  T  T baseline



CD DI   T S resist  CD baseline
 CD1   f1 O1 , O2 ...O7 

  ...   
...

CDn   f n O1 , O2 ...O7 
CD Offset
Model
• Seen as a constrained quadratic programming problem
T




  

• Minimize
 CD DI  CDt arget   CDDI  CDt arget 

• Subject to:
 
O Low  Oi  OUp
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
i  1,2...7
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Final Inspection (FI) CDU Control Methodology



CD DI   T S resist  CD baseline
• Plasma etching induced AW CD bias (signature)




CD ps  CD FI  CD DI
• Across-wafer FI CD is function of zone offsets



CD FI  CD DI  CD ps
• Minimize:
• Subject to:
T


 CD FI  CDt arget 




 g1 (O1 , O2 ...O7 ) 

 
...

 g n (O1 , O2 ...O7 )

 

 CDFI  CDt arget 


O Low  Oi  OUp
i  1,2...7
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FI CDU Control Verification Experiment Setup
• Focus on Pitch 250 L/S 1:1, plate B
• Use two-week-average FICD and bias signatures to generate offsets
• Verification experiment is done sequentially
• PEB adjustment is checked first to ensure it is close to the modelpredicted one
• DICD is then checked to ensure its correct adjustment
• FICD is finally checked
PEB
verification
Plate B (PEB
adjusted)
(Litho)
DICD
verification
Measure
DICD
FICD
verification
Chamber
(Etch)
Measure
FICD
6 wfrs
Verification experiment setup
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Long Term Overall Improvement ~35%
in recently completed experiment at AMD/SDC
across-wafer sigma of 250 1:1 lines, using CDSEM
Before
2.5
2
After
1.5
Series1
1
0.5
0
1
3
5
7
9
11
13
15
Confirmation Wafers (done six months after calibration)
σ=1.36nm
σ=1.21nm
σ=1.26nm
σ=1.14nm
σ=1.41nm
σ=1.39nm
m=141.9nm
m=142.1nm
m=141.7nm
m=141.5nm
m=141.4nm
m=142.4nm
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Verification experiment results
(before control vs. after control)
FI CDV before and after control
DI CDV before and after control
2.5
4.5
3.5
Wfr1
3
Wfr2
2.5
Wfr3
2
Wfr4
1.5
Wfr5
1
Wfr6
FI CDV 1 sigma(nm)
DI CDV 1 sigma (nm)
4
2
Wfr1
Wfr2
1.5
Wfr3
Wfr4
1
Wfr5
Wfr6
0.5
0.5
0
0
Before
After
Before
After
DICD uniformity is sacrificed in order to optimize FICD uniformity
Qiaolin (Charlie) Zhang, on internship at AMD/ Spansion 2005-06
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Data Mining for Yield Ramping (APC)
• What is it:
Exploit existing tool/wafer data
for control optimization
•
•
Basic Idea:
– Wafer Metrology alone has limited precision – enhance it by
combining tool/process/wafer data using multivariate techniques
– Identify basic operating fingerprints, and distinguish from
fingerprints in “rogue” situations
– Combine basic operating fingerprints to predictive models suitable
for APC
Potential Payoff:
– Faster, more disciplined yield ramp
– Rational deployment of metrology and control resources
– Leapfrog present metrology precision/accuracy limitations
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Example of Proposed Control Deployment
Process A
Model
Process B
Model
Recipe Model
Maintenance
Generate
Corrections
Control Decisions
Model-based
Controller
(supervisor decides on
feedback/feed-forward)
Model-based
Controller
Incoming Wafer
Process A
Process B
SPC & recipe
Filter
SPC & recipe
Filter
Production
Metrology
Outgoing
Wafer
Model
Maintenance
Physical Wafer
Measurements
Model Prediction of
Physical and Electrical Wafer parameters
Control Limits driving
control alarms
Process
Specifications
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Virtual Metrology Preview
Actual by Predi cted Pl ot VthPmos
0.2
-0.45
0.1
-0.5
AVEvtP Actual
AVEPmosIds at Actual
Actual by Predi cted Pl ot PmosIdsat
0
-0.1
-0.2
-0.3
-0.4
-0.4 -0.3 -0.2 -0.1
.0
.1
AVEPmosIdsat Predicted P<.0001
RSq=0.96 RMSE=0.0324
Summary of Fi t
RSquare
0.963795
RSquare Adj
0.939111
Root Mean Square Error
0.032425
Mean of Response
-0.11287
Observations (or Sum Wgts)
38
-0.55
-0.6
-0.65
-0.7
-0.75
.2
-0.8
-0.80
-0.70 -0.65 -0.60 -0.55 -0.50
AVEvtP Predicted P<.0001 RSq=0.96
RMSE=0.0155
Summary of Fi t
RSquare
0.960488
RSquare Adj
0.945854
Root Mean Square Error
0.015473
Mean of Response
-0.62092
Observations (or Sum Wgts)
38
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Outline
•
•
•
•
CD Control
CD Modeling
IC Performance Impact
New Directions
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Motivation
• Monte Carlo simulation:
Manuf. statistics
Manuf. statistics
2
Canonical circuit
μsys
rand
μ,
σ2,(x,y),
ρ(Δx,σΔy)
(ρμm(Δx, Δy))
spatial correlation
power
delay
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Decomposition of Spatial CD Variation
=
Average Wafer
+
+
Scaled Mask Errors
+
Across-Wafer Variation
Across-Field Variation
+
Die-to-Die Variation
“Random” Variation
J. Cain and C. Spanos, “Electrical linewidth metrology for systematic CD variation characterization and causal
analysis,” Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE vol. 5038,
pp. 350-361, 2003.
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Spatial Correlation & Process Control
• Calculation of spatial correlation,
before and following decomposition of
variance:


zi  xi  x / 
 jk 
 z
j

* zk / n
• Large(mm)-scale spatial correlation is largely accounted for by
systematic variation; smaller, (μm)-scale correlation may still have
structure, focus of current work
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Outline
•
•
•
•
CD Control
CD Modeling
IC Performance Impact
New Directions
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Digital Circuit Design and Sizing
• Digital Circuit Sizing Optimization Problem
– Goal: size the gates in a combinational logic circuit
– Minimize the effects of individual gate delay variations and
spatial correlations on the overall circuit delay
• Previous Work: Geometric Programming approach†
– Objective: min{maxp{allcircuitpaths} [ Di  k i ( D)]}
i p
where: Di = nominal delay for gate i
k = a constant ~ 2
††
 i (D)   ( xi 1/ 2 )Di derived from Pelgrom’s Model
with
model parameter γ
– Constraints: Fixed maximum total circuit area
†
S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International
Symposium on Microlithography, February 2006.
††
M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5,
pp.1433-1439, Oct. 1989.
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Performance Analysis
• 32-bit Ladner-Fisher adder circuit is sized and analyzed
– 459 gates, 3214 paths from input to output gates
• Monte Carlo analysis with 5000 samples
– RC model for nominal delay and a delay variation only due to vth
– Overall circuit delay statistics are
compared under two designs:
• Nominal Design, σ =0.88
• Statistical Design, σ =0.47
• Limitations
– gate delay variation depends only on Vth
– Ignored spatial correlations between the gates
† S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE
International Symposium on Microlithography, February 2006.
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More Comprehensive Designs
• Adding delay variation dependence on Leff in the
objective function:
min{maxp{allcircuitpaths} [ Di  k i ( D)]}
i p
where:  i ( D)   th ( xi 1/ 2 ) Di   Leff ( xi 1/ 2 ) Di
• Adding variation dependence on Leff and Spatial
Correlation
2 2
min{maxp{allcircuitpaths} [ Di  k i ( D)]  k
where:  i ( D)   th ( xi
i p
1/ 2
) Di   Leff ( xi
1/ 2
[  
i , j p ,i  j
ij
i
j
]}
) Di
ρij ≡ spatial correlation between gate i and j with separation dij
Large scale
model
1  d ij / X L (1   B ) d ij  X L

B
d ij  X L

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XL characteristic
correlation length
ρB characteristic
correlation baseline
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Monte Carlo Analysis on Circuit Delay
• 32-bit Ladner-Fisher adder circuit is analyzed
• Four types of Monte Carlo analysis are performed for each design
1. σ(D)~σ(Vth): gate delay variation results from σ(Vth)
2. σ(D)~σ(Vth)+sp.corr: gate delay variation results from σ(Vth) and
spatial correlations exist between the gates
3. σ(D)~σ(Vth)+σ(Leff): gate delay variation results from both σ(Vth)
and σ(Leff)
4. σ(D)~σ(Vth)+σ(Leff)+sp. corr: gate delay variation results from
σ(Vth), σ(Leff) and spatial correlations exits between the gates
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Simulation Results (5000 Monte Carlo Samples)
c) Min. delay var. due to Vth and Leff
frequency
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff)
+sp. corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff)
+sp. corr.
frequency
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff)
+sp. corr.
b) Minimize delay variations due to Vth
d) Min. delay var.delay
due to Vth, Leff and Spa. Corr.
(1) σ(D) ~ σ(Vth)
(2) σ(D) ~ σ(Vth)+sp.corr.
(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff)
+sp. corr.
frequency
frequency
a) Deterministic design objective
delay
delay
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Simulation Results
• Focus on the last analysis which considers both delay variations due to Vth
and Leff, and spatial correlations
a) Deterministic design
σ(D) = 3.02, yield = 63.42%
frequency
b) Minimize delay variations due to Vth
σ(D) = 1.96, yield = 92.06%
c) Min. delay var. due to Vth and Leff
σ(D) = 1.52, yield = 96.62%
d) Min. delay var. due to Vth, Leff and
spatial correlation
σ(D) = 1.36, yield = 98.22%
delay
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Outline
•
•
•
•
CD Control
CD Modeling
IC Performance Impact
New Directions
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Matching Properties of MOSFETs
•
•
Average value of the parameter over any area is
given by the integral of P(x,y) over this area.
Actual mismatch is given by the difference of
two integrals
L
(x12,y12)
W

1 

 (x1,y1)
P  x12 , y12  
  P  x ', y ' dx ' dy '   P  x ', y ' dx ' dy '
area 
area  x2 , y2 

area x1 , y1 

•
†
Dx (x2,y2)
x
This integral can be interpreted as the
convolution of a geometry function with the
“mismatch source” function P(x,y)
x1  x2
y y
, y12  1 2
2
2
D
D




 
G  x ', y '  BOX  x ' , y '   BOX  x ' , y ' 
1
P  x12 , y12  
P  x ', y ' G  x ' x12 , y ' y12  dx ' dy '
2
2




area  
 L L
 W W
for x    ,  , y    , 
1
BOX  x, y   
 2 2
 2 2
0
P x ,  y  G x ,  y  P x ,  y
else
x12 



 

† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solidstate Circuits, Vol.24, No. 5, pp.1433-1439, Oct. 1989.
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First Source of Variation – White Noise
• The events have a correlation distance much smaller than the
transistor dimensions.
• In Fourier domain it is a constant value for all spatial frequencies

2
 P  
 y 
1
4
2


 x 
y   x 
G  x ,  y   P  x ,  y  d x d y
2
2
• The assumption of short correlation distance implies that no relation
exists between matching and the spacing D between two transistors.
AP2
  P  
WL
2
But what if W and L are also variable?
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Additional Sources of Variation are Deterministic
•
•
Systematic error from across wafer variations
Systematic error from within field variations
–
–
–
–
Scanner optics / mechanics
Mask errors
Pattern densities (in Litho, Etch, CMP, Anneal, etc.)
And, of course, LER…
P
Wafer diameter
 2  P  SP2 Dx2 + ?
How do we deal with the complexity of the deterministic functions?
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Device Model and Yield under LER
Source
Li-1
Li
Li+1
Drain
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FinFET LER
Body
C
h
A
t
+
B
=
Gate
L
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FinFET LER
C
A
B
C
t
h
B
A
h
L
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FinFET LER Issues
• Hot carrier reliability
• Mobility degradation due to surface scattering
– Si FinFET vs. TFT
• Ioff and Ion variations due to LER
• Orientation effects
• Poly-Si vs. sc-Si
– TFT vs. bulk
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Transfer of LER
Resist
BARC
Hard Mask
Poly-Si
Gate Dielectric
Substrate
• Transfer of LER from resist
film onto underlying film is
a multi-step process
• Furthermore, the junction
edges of tip and halo
implants is redefine the
LER underneath the etched
gate stack
Schematic of a typical gate stack
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Outline
•
•
•
•
CD Control
CD Modeling
IC Performance Impact
New Directions
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In Summary
• CD (and many other, equally critical elements)
vary in a complex manner
• We are observability- and controllability-limited
• Major efforts are under way to
– Enhance the metrology capability
– Reform and expand the models of variability
– Incorporate variability modeling into DFM tool
• We are bringing in enhanced CD metrology
capability by the donation of the Timbre/TEL
ODP tool
BCAM
7/17/2015